blob: 9b0dd9a8553d89f74574d2304035c3c815c84cff [file] [log] [blame]
Raul E Rangelb3c41322020-05-20 14:07:41 -06001# SPDX-License-Identifier: GPL-2.0-or-later
2chip soc/amd/picasso
3
4 # Set FADT Configuration
Raul E Rangelb3c41322020-05-20 14:07:41 -06005 register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
Felix Held5ad4dcb2020-08-13 01:27:39 +02006 # See table 5-34 ACPI 6.3 spec
7 register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE"
Raul E Rangelb3c41322020-05-20 14:07:41 -06008
9 register "acp_pin_cfg" = "I2S_PINS_I2S_TDM"
Furquan Shaikhfd884082020-08-11 17:05:46 -070010 register "acp_i2s_wake_enable" = "0"
Felix Held828a36e2020-09-11 21:45:20 +020011 register "acp_pme_enable" = "0"
Raul E Rangelb3c41322020-05-20 14:07:41 -060012
13 # Start : OPN Performance Configuration
14 # (Configuratin that is common for all variants)
15 # For the below fields, 0 indicates use SOC default
16
17 # PROCHOT_L de-assertion Ramp Time
Zheng Bao795d73c2020-10-27 15:36:55 +080018 register "prochot_l_deassertion_ramp_time_ms" = "20"
Raul E Rangelb3c41322020-05-20 14:07:41 -060019
20 # Lower die temperature limit
Zheng Bao795d73c2020-10-27 15:36:55 +080021 register "thermctl_limit_degreeC" = "100"
Raul E Rangelb3c41322020-05-20 14:07:41 -060022
23 # FP5 Processor Voltage Supply PSI Currents
Zheng Bao795d73c2020-10-27 15:36:55 +080024 register "psi0_current_limit_mA" = "18000"
25 register "psi0_soc_current_limit_mA" = "12000"
26 register "vddcr_soc_voltage_margin_mV" = "0"
27 register "vddcr_vdd_voltage_margin_mV" = "0"
Raul E Rangelb3c41322020-05-20 14:07:41 -060028
29 # VRM Limits
Zheng Bao795d73c2020-10-27 15:36:55 +080030 register "vrm_maximum_current_limit_mA" = "0"
31 register "vrm_soc_maximum_current_limit_mA" = "0"
32 register "vrm_current_limit_mA" = "0"
33 register "vrm_soc_current_limit_mA" = "0"
Raul E Rangelb3c41322020-05-20 14:07:41 -060034
35 # Misc SMU settings
36 register "sb_tsi_alert_comparator_mode_en" = "0"
37 register "core_dldo_bypass" = "1"
38 register "min_soc_vid_offset" = "0"
39 register "aclk_dpm0_freq_400MHz" = "0"
40
41 # End : OPN Performance Configuration
42
Raul E Rangel7c79d832020-09-03 14:30:33 -060043 register "emmc_config" = "{
44 .timing = SD_EMMC_EMMC_HS400,
Raul E Rangel94be1f72020-09-03 15:46:56 -060045 .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A,
46 /*
47 * The reference design was missing a pull-up on the CMD line.
48 * This means we can't run at the full 400 kHz. By setting this
49 * to 1 we run at the slowest frequency possible by the
50 * controller (~97 kHz).
51 *
52 * Boards that have the pull-up should correctly set this.
53 */
54 .init_khz_preset = 1,
Raul E Rangel7c79d832020-09-03 14:30:33 -060055 }"
Raul E Rangelb3c41322020-05-20 14:07:41 -060056
Felix Held1d0154c2020-07-23 19:37:42 +020057 register "has_usb2_phy_tune_params" = "1"
58
Chris Wang1e3e5282020-06-23 21:10:57 +080059 # Controller0 Port0 Default
Felix Held3a7389e2020-07-23 18:22:30 +020060 register "usb_2_port_tune_params[0]" = "{
Chris Wang1e3e5282020-06-23 21:10:57 +080061 .com_pds_tune = 0x03,
62 .sq_rx_tune = 0x3,
63 .tx_fsls_tune = 0x3,
64 .tx_pre_emp_amp_tune = 0x03,
65 .tx_pre_emp_pulse_tune = 0x0,
66 .tx_rise_tune = 0x1,
Kevin Chiude20b282020-11-19 14:09:47 +080067 .tx_vref_tune = 0x6,
Chris Wang1e3e5282020-06-23 21:10:57 +080068 .tx_hsxv_tune = 0x3,
69 .tx_res_tune = 0x01,
70 }"
71
72 # Controller0 Port1 Default
Felix Held3a7389e2020-07-23 18:22:30 +020073 register "usb_2_port_tune_params[1]" = "{
Chris Wang1e3e5282020-06-23 21:10:57 +080074 .com_pds_tune = 0x03,
75 .sq_rx_tune = 0x3,
76 .tx_fsls_tune = 0x3,
77 .tx_pre_emp_amp_tune = 0x03,
78 .tx_pre_emp_pulse_tune = 0x0,
79 .tx_rise_tune = 0x1,
Kevin Chiude20b282020-11-19 14:09:47 +080080 .tx_vref_tune = 0x6,
Chris Wang1e3e5282020-06-23 21:10:57 +080081 .tx_hsxv_tune = 0x3,
82 .tx_res_tune = 0x01,
83 }"
84
85 # Controller0 Port2 Default
Felix Held3a7389e2020-07-23 18:22:30 +020086 register "usb_2_port_tune_params[2]" = "{
Chris Wang1e3e5282020-06-23 21:10:57 +080087 .com_pds_tune = 0x03,
88 .sq_rx_tune = 0x3,
89 .tx_fsls_tune = 0x3,
90 .tx_pre_emp_amp_tune = 0x03,
91 .tx_pre_emp_pulse_tune = 0x0,
92 .tx_rise_tune = 0x1,
Kevin Chiude20b282020-11-19 14:09:47 +080093 .tx_vref_tune = 0x6,
Chris Wang1e3e5282020-06-23 21:10:57 +080094 .tx_hsxv_tune = 0x3,
95 .tx_res_tune = 0x01,
96 }"
97
98 # Controller0 Port3 Default
Felix Held3a7389e2020-07-23 18:22:30 +020099 register "usb_2_port_tune_params[3]" = "{
Chris Wang1e3e5282020-06-23 21:10:57 +0800100 .com_pds_tune = 0x03,
101 .sq_rx_tune = 0x3,
102 .tx_fsls_tune = 0x3,
103 .tx_pre_emp_amp_tune = 0x03,
104 .tx_pre_emp_pulse_tune = 0x0,
105 .tx_rise_tune = 0x1,
Kevin Chiude20b282020-11-19 14:09:47 +0800106 .tx_vref_tune = 0x6,
Chris Wang1e3e5282020-06-23 21:10:57 +0800107 .tx_hsxv_tune = 0x3,
108 .tx_res_tune = 0x01,
109 }"
110
111 # Controller1 Port0 Default
Felix Held3a7389e2020-07-23 18:22:30 +0200112 register "usb_2_port_tune_params[4]" = "{
Chris Wang1e3e5282020-06-23 21:10:57 +0800113 .com_pds_tune = 0x03,
114 .sq_rx_tune = 0x3,
115 .tx_fsls_tune = 0x3,
116 .tx_pre_emp_amp_tune = 0x02,
117 .tx_pre_emp_pulse_tune = 0x0,
118 .tx_rise_tune = 0x1,
Kevin Chiude20b282020-11-19 14:09:47 +0800119 .tx_vref_tune = 0x5,
Chris Wang1e3e5282020-06-23 21:10:57 +0800120 .tx_hsxv_tune = 0x3,
121 .tx_res_tune = 0x01,
122 }"
123
124 # Controller1 Port1 Default
Felix Held3a7389e2020-07-23 18:22:30 +0200125 register "usb_2_port_tune_params[5]" = "{
Chris Wang1e3e5282020-06-23 21:10:57 +0800126 .com_pds_tune = 0x03,
127 .sq_rx_tune = 0x3,
128 .tx_fsls_tune = 0x3,
129 .tx_pre_emp_amp_tune = 0x02,
130 .tx_pre_emp_pulse_tune = 0x0,
131 .tx_rise_tune = 0x1,
Kevin Chiude20b282020-11-19 14:09:47 +0800132 .tx_vref_tune = 0x5,
Chris Wang1e3e5282020-06-23 21:10:57 +0800133 .tx_hsxv_tune = 0x3,
134 .tx_res_tune = 0x01,
135 }"
136
Chris Wang68d68f12021-02-03 04:32:06 +0800137 # Start RV2 USB3 PHY Parameters
138 register "usb3_phy_override" = "0"
139
140 # USB3 Port0 Default
141 register "usb3_phy_tune_params[0]" = "{
142 .rx_eq_delta_iq_ovrd_val = 0x0,
143 .rx_eq_delta_iq_ovrd_en = 0x0,
144 }"
145
146 # USB3 Port1 Default
147 register "usb3_phy_tune_params[1]" = "{
148 .rx_eq_delta_iq_ovrd_val = 0x0,
149 .rx_eq_delta_iq_ovrd_en = 0x0,
150 }"
151
152 # USB3 Port2 Default
153 register "usb3_phy_tune_params[2]" = "{
154 .rx_eq_delta_iq_ovrd_val = 0x0,
155 .rx_eq_delta_iq_ovrd_en = 0x0,
156 }"
157
158 # USB3 Port3 Default
159 register "usb3_phy_tune_params[3]" = "{
160 .rx_eq_delta_iq_ovrd_val = 0x0,
161 .rx_eq_delta_iq_ovrd_en = 0x0,
162 }"
163
164 # SUP_DIG_LVL_OVRD_IN Default
165 register "usb3_rx_vref_ctrl" = "0x10"
166 register "usb3_rx_vref_ctrl_en" = "0x00"
167 register "usb_3_tx_vboost_lvl" = "0x07"
168 register "usb_3_tx_vboost_lvl_en" = "0x00"
169
170 # SUPX_DIG_LVL_OVRD_IN Default
171 register "usb_3_rx_vref_ctrl_x" = "0x10"
172 register "usb_3_rx_vref_ctrl_en_x" = "0x00"
173 register "usb_3_tx_vboost_lvl_x" = "0x07"
174 register "usb_3_tx_vboost_lvl_en_x" = "0x00"
175
176 # End RV2 USB3 phy setting
177
Felix Helde2379962020-07-29 01:02:38 +0200178 # USB OC pin mapping
179 register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0
180 register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1
181 register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" # USB A0
182 register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB A1
183 register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera
184 register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth
185
Raul E Rangelb3c41322020-05-20 14:07:41 -0600186 # SPI Configuration
187 register "common_config.spi_config" = "{
Rob Barnes13ec6a02020-07-14 13:23:43 -0600188 .normal_speed = SPI_SPEED_33M, /* MHz */
189 .fast_speed = SPI_SPEED_66M, /* MHz */
Raul E Rangelb3c41322020-05-20 14:07:41 -0600190 .altio_speed = SPI_SPEED_66M, /* MHz */
191 .tpm_speed = SPI_SPEED_66M, /* MHz */
Martin Roth637f9412020-07-06 20:02:36 -0600192 .read_mode = SPI_READ_MODE_DUAL122,
Raul E Rangelb3c41322020-05-20 14:07:41 -0600193 }"
194
195 # eSPI Configuration
196 register "common_config.espi_config" = "{
197 .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
198 .generic_io_range[0] = {
199 .base = 0x62,
200 /*
201 * Only 0x62 and 0x66 are required. But, this is not supported by
202 * standard IO decodes and there are only 4 generic I/O windows
203 * available. Hence, open a window from 0x62-0x67.
204 */
205 .size = 5,
206 },
207 .generic_io_range[1] = {
208 .base = 0x800, /* EC_HOST_CMD_REGION0 */
209 .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */
210 },
211 .generic_io_range[2] = {
212 .base = 0x900, /* EC_LPC_ADDR_MEMMAP */
213 .size = 255, /* EC_MEMMAP_SIZE */
214 },
215 .generic_io_range[3] = {
216 .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */
217 .size = 8, /* 0x200 - 0x207 */
218 },
219
220 .io_mode = ESPI_IO_MODE_QUAD,
221 .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
222 .crc_check_enable = 1,
223 .dedicated_alert_pin = 1,
224 .periph_ch_en = 1,
225 .vw_ch_en = 1,
226 .oob_ch_en = 0,
227 .flash_ch_en = 0,
228
Aaron Durbin76fcf8292020-07-02 11:08:21 -0600229 .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
Raul E Rangelb3c41322020-05-20 14:07:41 -0600230 }"
231
232 register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
233
Felix Heldd555d6a2020-08-28 02:12:52 +0200234 # genral purpose PCIe clock output configuration
235 register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
236 register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
237 register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD
238 register "gpp_clk_config[3]" = "GPP_CLK_OFF"
239 register "gpp_clk_config[4]" = "GPP_CLK_OFF"
240 register "gpp_clk_config[5]" = "GPP_CLK_OFF"
241 register "gpp_clk_config[6]" = "GPP_CLK_OFF"
242
Raul E Rangelb3c41322020-05-20 14:07:41 -0600243 device cpu_cluster 0 on
244 device lapic 0 on end
245 end
246
247 # See AMD 55570-B1 Table 13: PCI Device ID Assignments.
248 device domain 0 on
249 subsystemid 0x1022 0x1510 inherit
250 device pci 0.0 on end # Root Complex
251 device pci 0.2 on end # IOMMU
252 device pci 1.0 on end # Dummy Host Bridge, must be enabled
253 device pci 1.1 off end # GPP Bridge 0
Rob Barnesd1095c72020-09-25 14:16:46 -0600254 device pci 1.2 on # GPP Bridge 1 - Wifi
255 chip drivers/wifi/generic
256 register "wake" = "GEVENT_8"
257 device pci 00.0 on end
258 end
259 end
Raul E Rangelb3c41322020-05-20 14:07:41 -0600260 device pci 1.3 on end # GPP Bridge 2 - SD
261 device pci 1.4 off end # GPP Bridge 3
262 device pci 1.5 off end # GPP Bridge 4
263 device pci 8.0 on end # Dummy Host Bridge, must be enabled
264 device pci 8.1 on # Internal GPP Bridge 0 to Bus A
265 device pci 0.0 on end # Internal GPU
266 device pci 0.1 on end # Display HDA
267 device pci 0.2 on end # Crypto Coprocesor
Rob Barnesf0d1c9a2020-06-24 09:42:02 -0600268 device pci 0.3 on # USB 3.1
269 chip drivers/usb/acpi
270 register "desc" = ""Root Hub""
271 register "type" = "UPC_TYPE_HUB"
272 device usb 0.0 on
273 chip drivers/usb/acpi
274 register "desc" = ""Left Type-C Port""
275 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
276 register "group" = "ACPI_PLD_GROUP(1, 1)"
277 device usb 2.0 on end
278 end
279 chip drivers/usb/acpi
280 register "desc" = ""Right Type-C Port""
281 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
282 register "group" = "ACPI_PLD_GROUP(2, 2)"
283 device usb 2.1 on end
284 end
285 chip drivers/usb/acpi
286 register "desc" = ""Left Type-A Port""
287 register "type" = "UPC_TYPE_USB3_A"
288 register "group" = "ACPI_PLD_GROUP(1, 2)"
289 device usb 2.2 on end
290 end
291 chip drivers/usb/acpi
292 register "desc" = ""Right Type-A Port""
293 register "type" = "UPC_TYPE_USB3_A"
294 register "group" = "ACPI_PLD_GROUP(2, 1)"
295 device usb 2.3 on end
296 end
297 chip drivers/usb/acpi
298 register "desc" = ""User-Facing Camera""
299 register "type" = "UPC_TYPE_INTERNAL"
300 device usb 2.4 on end
301 end
302 chip drivers/usb/acpi
303 register "desc" = ""Bluetooth""
304 register "type" = "UPC_TYPE_INTERNAL"
Rob Barnes56e889c2020-07-23 14:21:23 -0600305 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)"
Rob Barnesf0d1c9a2020-06-24 09:42:02 -0600306 device usb 2.5 on end
307 end
308 chip drivers/usb/acpi
309 register "desc" = ""Left Type-C Port""
310 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
311 register "group" = "ACPI_PLD_GROUP(1, 1)"
312 device usb 3.0 on end
313 end
314 chip drivers/usb/acpi
315 register "desc" = ""Right Type-C Port""
316 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
317 register "group" = "ACPI_PLD_GROUP(2, 2)"
318 device usb 3.1 on end
319 end
320 chip drivers/usb/acpi
321 register "desc" = ""Left Type-A Port""
322 register "type" = "UPC_TYPE_USB3_A"
323 register "group" = "ACPI_PLD_GROUP(1, 2)"
324 device usb 3.2 on end
325 end
326 chip drivers/usb/acpi
327 register "desc" = ""Right Type-A Port""
328 register "type" = "UPC_TYPE_USB3_A"
329 register "group" = "ACPI_PLD_GROUP(2, 1)"
330 device usb 3.3 on end
331 end
332 end
333 end
334 end
Furquan Shaikh24ec79c2020-07-16 13:40:28 -0700335 device pci 0.5 on
336 chip drivers/amd/i2s_machine_dev
337 register "hid" = ""AMDI5682""
338 # DMIC select GPIO for ACP machine device
339 # This GPIO is used to select DMIC0 or DMIC1 by the
340 # kernel driver. It does not really have a polarity
341 # since low and high control the selection of DMIC and
342 # hence does not have an active polarity.
343 # Kernel driver does not use the polarity field and
344 # instead treats the GPIO selection as follows:
345 # Set low (0) = Select DMIC0
346 # Set high (1) = Select DMIC1
347 register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)"
348 device generic 0.0 on end
349 end
350 end # Audio
Felix Held90ca7f42020-08-21 16:17:05 +0200351 device pci 0.6 off end # HDA
Raul E Rangelb3c41322020-05-20 14:07:41 -0600352 device pci 0.7 on end # non-Sensor Fusion Hub device
353 end
Matt Papageorge48b2b2b2020-07-30 15:32:34 -0500354 device pci 8.2 off # Internal GPP Bridge 0 to Bus B
355 device pci 0.0 off end # AHCI
Raul E Rangelb3c41322020-05-20 14:07:41 -0600356 end
357 device pci 14.0 on end # SM
358 device pci 14.3 on # - D14F3 bridge
359 chip ec/google/chromeec
360 device pnp 0c09.0 on
361 chip ec/google/chromeec/i2c_tunnel
362 register "uid" = "1"
363 register "remote_bus" = "8"
364 device generic 0.0 on
365 chip drivers/i2c/generic
366 register "hid" = ""10EC5682""
367 register "name" = ""RT58""
368 register "uid" = "1"
369 register "desc" = ""Realtek RT5682""
Josie Nordrumcc72e152020-08-03 11:39:41 -0600370 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)"
Akshu Agrawalc7d6d7a2020-07-06 19:39:51 +0530371 register "property_count" = "2"
Raul E Rangelb3c41322020-05-20 14:07:41 -0600372 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
373 register "property_list[0].name" = ""realtek,jd-src""
374 register "property_list[0].integer" = "1"
Akshu Agrawalc7d6d7a2020-07-06 19:39:51 +0530375 register "property_list[1].type" = "ACPI_DP_TYPE_STRING"
376 register "property_list[1].name" = ""realtek,mclk-name""
377 register "property_list[1].string" = ""oscout1""
Raul E Rangelb3c41322020-05-20 14:07:41 -0600378 device i2c 1a on end
379 end
380 end
381 end
Furquan Shaikhe284bff2020-07-02 16:03:06 -0700382 chip ec/google/chromeec/audio_codec
383 register "uid" = "1"
384 device generic 0 on end
385 end
Raul E Rangelb3c41322020-05-20 14:07:41 -0600386 end
387 end
388 end
389 device pci 18.0 on end # Data fabric [0-7]
390 device pci 18.1 on end
391 device pci 18.2 on end
392 device pci 18.3 on end
393 device pci 18.4 on end
394 device pci 18.5 on end
395 device pci 18.6 on end
396 end # domain
397
398 chip drivers/generic/max98357a
Raul E Rangel19704cd2020-06-02 10:43:20 -0600399 register "hid" = ""MX98357A""
Raul E Rangelb3c41322020-05-20 14:07:41 -0600400 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)"
401 register "sdmode_delay" = "5"
402 device generic 0.1 on end
403 end
404
405 device mmio 0xfedc5000 on
406 chip drivers/i2c/tpm
407 register "hid" = ""GOOG0005""
408 register "desc" = ""Cr50 TPM""
409 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
410 device i2c 50 on end
411 end
412 end
413
Raul E Rangel5e29c0e2020-06-12 11:41:16 -0600414 device mmio 0xfedca000 off end # UART1
415 device mmio 0xfedce000 off end # UART2
416 device mmio 0xfedcf000 off end # UART3
417
Raul E Rangelb3c41322020-05-20 14:07:41 -0600418end # chip soc/amd/picasso