mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree
BUG=b:149970243
BRANCH=zork
Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index c761602..42219d7 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -180,6 +180,15 @@
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+ # genral purpose PCIe clock output configuration
+ register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
+ register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
+ register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD
+ register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+ register "gpp_clk_config[4]" = "GPP_CLK_OFF"
+ register "gpp_clk_config[5]" = "GPP_CLK_OFF"
+ register "gpp_clk_config[6]" = "GPP_CLK_OFF"
+
device cpu_cluster 0 on
device lapic 0 on end
end