Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | chip soc/amd/picasso |
| 3 | |
| 4 | # Set FADT Configuration |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 5 | register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" |
Felix Held | 5ad4dcb | 2020-08-13 01:27:39 +0200 | [diff] [blame] | 6 | # See table 5-34 ACPI 6.3 spec |
| 7 | register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 8 | |
| 9 | register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" |
Furquan Shaikh | fd88408 | 2020-08-11 17:05:46 -0700 | [diff] [blame] | 10 | register "acp_i2s_wake_enable" = "0" |
Felix Held | 828a36e | 2020-09-11 21:45:20 +0200 | [diff] [blame] | 11 | register "acp_pme_enable" = "0" |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 12 | |
| 13 | # Start : OPN Performance Configuration |
| 14 | # (Configuratin that is common for all variants) |
| 15 | # For the below fields, 0 indicates use SOC default |
| 16 | |
| 17 | # PROCHOT_L de-assertion Ramp Time |
| 18 | register "prochot_l_deassertion_ramp_time" = "20" #mS |
| 19 | |
| 20 | # Lower die temperature limit |
| 21 | register "thermctl_limit" = "100" #degrees C |
| 22 | |
| 23 | # FP5 Processor Voltage Supply PSI Currents |
| 24 | register "psi0_current_limit" = "18000" #mA |
| 25 | register "psi0_soc_current_limit" = "12000" #mA |
| 26 | register "vddcr_soc_voltage_margin" = "0" #mV |
| 27 | register "vddcr_vdd_voltage_margin" = "0" #mV |
| 28 | |
| 29 | # VRM Limits |
| 30 | register "vrm_maximum_current_limit" = "0" #mA |
| 31 | register "vrm_soc_maximum_current_limit" = "0" #mA |
| 32 | register "vrm_current_limit" = "0" #mA |
| 33 | register "vrm_soc_current_limit" = "0" #mA |
| 34 | |
| 35 | # Misc SMU settings |
| 36 | register "sb_tsi_alert_comparator_mode_en" = "0" |
| 37 | register "core_dldo_bypass" = "1" |
| 38 | register "min_soc_vid_offset" = "0" |
| 39 | register "aclk_dpm0_freq_400MHz" = "0" |
| 40 | |
| 41 | # End : OPN Performance Configuration |
| 42 | |
Raul E Rangel | 7c79d83 | 2020-09-03 14:30:33 -0600 | [diff] [blame] | 43 | register "emmc_config" = "{ |
| 44 | .timing = SD_EMMC_EMMC_HS400, |
Raul E Rangel | 94be1f7 | 2020-09-03 15:46:56 -0600 | [diff] [blame] | 45 | .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, |
| 46 | /* |
| 47 | * The reference design was missing a pull-up on the CMD line. |
| 48 | * This means we can't run at the full 400 kHz. By setting this |
| 49 | * to 1 we run at the slowest frequency possible by the |
| 50 | * controller (~97 kHz). |
| 51 | * |
| 52 | * Boards that have the pull-up should correctly set this. |
| 53 | */ |
| 54 | .init_khz_preset = 1, |
Raul E Rangel | 7c79d83 | 2020-09-03 14:30:33 -0600 | [diff] [blame] | 55 | }" |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 56 | |
Felix Held | 1d0154c | 2020-07-23 19:37:42 +0200 | [diff] [blame] | 57 | register "has_usb2_phy_tune_params" = "1" |
| 58 | |
Chris Wang | 1e3e528 | 2020-06-23 21:10:57 +0800 | [diff] [blame] | 59 | # Controller0 Port0 Default |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 60 | register "usb_2_port_tune_params[0]" = "{ |
Chris Wang | 1e3e528 | 2020-06-23 21:10:57 +0800 | [diff] [blame] | 61 | .com_pds_tune = 0x03, |
| 62 | .sq_rx_tune = 0x3, |
| 63 | .tx_fsls_tune = 0x3, |
| 64 | .tx_pre_emp_amp_tune = 0x03, |
| 65 | .tx_pre_emp_pulse_tune = 0x0, |
| 66 | .tx_rise_tune = 0x1, |
| 67 | .rx_vref_tune = 0x6, |
| 68 | .tx_hsxv_tune = 0x3, |
| 69 | .tx_res_tune = 0x01, |
| 70 | }" |
| 71 | |
| 72 | # Controller0 Port1 Default |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 73 | register "usb_2_port_tune_params[1]" = "{ |
Chris Wang | 1e3e528 | 2020-06-23 21:10:57 +0800 | [diff] [blame] | 74 | .com_pds_tune = 0x03, |
| 75 | .sq_rx_tune = 0x3, |
| 76 | .tx_fsls_tune = 0x3, |
| 77 | .tx_pre_emp_amp_tune = 0x03, |
| 78 | .tx_pre_emp_pulse_tune = 0x0, |
| 79 | .tx_rise_tune = 0x1, |
| 80 | .rx_vref_tune = 0x6, |
| 81 | .tx_hsxv_tune = 0x3, |
| 82 | .tx_res_tune = 0x01, |
| 83 | }" |
| 84 | |
| 85 | # Controller0 Port2 Default |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 86 | register "usb_2_port_tune_params[2]" = "{ |
Chris Wang | 1e3e528 | 2020-06-23 21:10:57 +0800 | [diff] [blame] | 87 | .com_pds_tune = 0x03, |
| 88 | .sq_rx_tune = 0x3, |
| 89 | .tx_fsls_tune = 0x3, |
| 90 | .tx_pre_emp_amp_tune = 0x03, |
| 91 | .tx_pre_emp_pulse_tune = 0x0, |
| 92 | .tx_rise_tune = 0x1, |
| 93 | .rx_vref_tune = 0x6, |
| 94 | .tx_hsxv_tune = 0x3, |
| 95 | .tx_res_tune = 0x01, |
| 96 | }" |
| 97 | |
| 98 | # Controller0 Port3 Default |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 99 | register "usb_2_port_tune_params[3]" = "{ |
Chris Wang | 1e3e528 | 2020-06-23 21:10:57 +0800 | [diff] [blame] | 100 | .com_pds_tune = 0x03, |
| 101 | .sq_rx_tune = 0x3, |
| 102 | .tx_fsls_tune = 0x3, |
| 103 | .tx_pre_emp_amp_tune = 0x03, |
| 104 | .tx_pre_emp_pulse_tune = 0x0, |
| 105 | .tx_rise_tune = 0x1, |
| 106 | .rx_vref_tune = 0x6, |
| 107 | .tx_hsxv_tune = 0x3, |
| 108 | .tx_res_tune = 0x01, |
| 109 | }" |
| 110 | |
| 111 | # Controller1 Port0 Default |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 112 | register "usb_2_port_tune_params[4]" = "{ |
Chris Wang | 1e3e528 | 2020-06-23 21:10:57 +0800 | [diff] [blame] | 113 | .com_pds_tune = 0x03, |
| 114 | .sq_rx_tune = 0x3, |
| 115 | .tx_fsls_tune = 0x3, |
| 116 | .tx_pre_emp_amp_tune = 0x02, |
| 117 | .tx_pre_emp_pulse_tune = 0x0, |
| 118 | .tx_rise_tune = 0x1, |
| 119 | .rx_vref_tune = 0x5, |
| 120 | .tx_hsxv_tune = 0x3, |
| 121 | .tx_res_tune = 0x01, |
| 122 | }" |
| 123 | |
| 124 | # Controller1 Port1 Default |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 125 | register "usb_2_port_tune_params[5]" = "{ |
Chris Wang | 1e3e528 | 2020-06-23 21:10:57 +0800 | [diff] [blame] | 126 | .com_pds_tune = 0x03, |
| 127 | .sq_rx_tune = 0x3, |
| 128 | .tx_fsls_tune = 0x3, |
| 129 | .tx_pre_emp_amp_tune = 0x02, |
| 130 | .tx_pre_emp_pulse_tune = 0x0, |
| 131 | .tx_rise_tune = 0x1, |
| 132 | .rx_vref_tune = 0x5, |
| 133 | .tx_hsxv_tune = 0x3, |
| 134 | .tx_res_tune = 0x01, |
| 135 | }" |
| 136 | |
Felix Held | e237996 | 2020-07-29 01:02:38 +0200 | [diff] [blame] | 137 | # USB OC pin mapping |
| 138 | register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 |
| 139 | register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1 |
| 140 | register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" # USB A0 |
| 141 | register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB A1 |
| 142 | register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera |
| 143 | register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth |
| 144 | |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 145 | # SPI Configuration |
| 146 | register "common_config.spi_config" = "{ |
Rob Barnes | 13ec6a0 | 2020-07-14 13:23:43 -0600 | [diff] [blame] | 147 | .normal_speed = SPI_SPEED_33M, /* MHz */ |
| 148 | .fast_speed = SPI_SPEED_66M, /* MHz */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 149 | .altio_speed = SPI_SPEED_66M, /* MHz */ |
| 150 | .tpm_speed = SPI_SPEED_66M, /* MHz */ |
Martin Roth | 637f941 | 2020-07-06 20:02:36 -0600 | [diff] [blame] | 151 | .read_mode = SPI_READ_MODE_DUAL122, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 152 | }" |
| 153 | |
| 154 | # eSPI Configuration |
| 155 | register "common_config.espi_config" = "{ |
| 156 | .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, |
| 157 | .generic_io_range[0] = { |
| 158 | .base = 0x62, |
| 159 | /* |
| 160 | * Only 0x62 and 0x66 are required. But, this is not supported by |
| 161 | * standard IO decodes and there are only 4 generic I/O windows |
| 162 | * available. Hence, open a window from 0x62-0x67. |
| 163 | */ |
| 164 | .size = 5, |
| 165 | }, |
| 166 | .generic_io_range[1] = { |
| 167 | .base = 0x800, /* EC_HOST_CMD_REGION0 */ |
| 168 | .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ |
| 169 | }, |
| 170 | .generic_io_range[2] = { |
| 171 | .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ |
| 172 | .size = 255, /* EC_MEMMAP_SIZE */ |
| 173 | }, |
| 174 | .generic_io_range[3] = { |
| 175 | .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ |
| 176 | .size = 8, /* 0x200 - 0x207 */ |
| 177 | }, |
| 178 | |
| 179 | .io_mode = ESPI_IO_MODE_QUAD, |
| 180 | .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, |
| 181 | .crc_check_enable = 1, |
| 182 | .dedicated_alert_pin = 1, |
| 183 | .periph_ch_en = 1, |
| 184 | .vw_ch_en = 1, |
| 185 | .oob_ch_en = 0, |
| 186 | .flash_ch_en = 0, |
| 187 | |
Aaron Durbin | 76fcf829 | 2020-07-02 11:08:21 -0600 | [diff] [blame] | 188 | .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 189 | }" |
| 190 | |
| 191 | register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" |
| 192 | |
Felix Held | d555d6a | 2020-08-28 02:12:52 +0200 | [diff] [blame] | 193 | # genral purpose PCIe clock output configuration |
| 194 | register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN |
| 195 | register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader |
| 196 | register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD |
| 197 | register "gpp_clk_config[3]" = "GPP_CLK_OFF" |
| 198 | register "gpp_clk_config[4]" = "GPP_CLK_OFF" |
| 199 | register "gpp_clk_config[5]" = "GPP_CLK_OFF" |
| 200 | register "gpp_clk_config[6]" = "GPP_CLK_OFF" |
| 201 | |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 202 | device cpu_cluster 0 on |
| 203 | device lapic 0 on end |
| 204 | end |
| 205 | |
| 206 | # See AMD 55570-B1 Table 13: PCI Device ID Assignments. |
| 207 | device domain 0 on |
| 208 | subsystemid 0x1022 0x1510 inherit |
| 209 | device pci 0.0 on end # Root Complex |
| 210 | device pci 0.2 on end # IOMMU |
| 211 | device pci 1.0 on end # Dummy Host Bridge, must be enabled |
| 212 | device pci 1.1 off end # GPP Bridge 0 |
Rob Barnes | d1095c7 | 2020-09-25 14:16:46 -0600 | [diff] [blame^] | 213 | device pci 1.2 on # GPP Bridge 1 - Wifi |
| 214 | chip drivers/wifi/generic |
| 215 | register "wake" = "GEVENT_8" |
| 216 | device pci 00.0 on end |
| 217 | end |
| 218 | end |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 219 | device pci 1.3 on end # GPP Bridge 2 - SD |
| 220 | device pci 1.4 off end # GPP Bridge 3 |
| 221 | device pci 1.5 off end # GPP Bridge 4 |
| 222 | device pci 8.0 on end # Dummy Host Bridge, must be enabled |
| 223 | device pci 8.1 on # Internal GPP Bridge 0 to Bus A |
| 224 | device pci 0.0 on end # Internal GPU |
| 225 | device pci 0.1 on end # Display HDA |
| 226 | device pci 0.2 on end # Crypto Coprocesor |
Rob Barnes | f0d1c9a | 2020-06-24 09:42:02 -0600 | [diff] [blame] | 227 | device pci 0.3 on # USB 3.1 |
| 228 | chip drivers/usb/acpi |
| 229 | register "desc" = ""Root Hub"" |
| 230 | register "type" = "UPC_TYPE_HUB" |
| 231 | device usb 0.0 on |
| 232 | chip drivers/usb/acpi |
| 233 | register "desc" = ""Left Type-C Port"" |
| 234 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 235 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 236 | device usb 2.0 on end |
| 237 | end |
| 238 | chip drivers/usb/acpi |
| 239 | register "desc" = ""Right Type-C Port"" |
| 240 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 241 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 242 | device usb 2.1 on end |
| 243 | end |
| 244 | chip drivers/usb/acpi |
| 245 | register "desc" = ""Left Type-A Port"" |
| 246 | register "type" = "UPC_TYPE_USB3_A" |
| 247 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 248 | device usb 2.2 on end |
| 249 | end |
| 250 | chip drivers/usb/acpi |
| 251 | register "desc" = ""Right Type-A Port"" |
| 252 | register "type" = "UPC_TYPE_USB3_A" |
| 253 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 254 | device usb 2.3 on end |
| 255 | end |
| 256 | chip drivers/usb/acpi |
| 257 | register "desc" = ""User-Facing Camera"" |
| 258 | register "type" = "UPC_TYPE_INTERNAL" |
| 259 | device usb 2.4 on end |
| 260 | end |
| 261 | chip drivers/usb/acpi |
| 262 | register "desc" = ""Bluetooth"" |
| 263 | register "type" = "UPC_TYPE_INTERNAL" |
Rob Barnes | 56e889c | 2020-07-23 14:21:23 -0600 | [diff] [blame] | 264 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)" |
Rob Barnes | f0d1c9a | 2020-06-24 09:42:02 -0600 | [diff] [blame] | 265 | device usb 2.5 on end |
| 266 | end |
| 267 | chip drivers/usb/acpi |
| 268 | register "desc" = ""Left Type-C Port"" |
| 269 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 270 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 271 | device usb 3.0 on end |
| 272 | end |
| 273 | chip drivers/usb/acpi |
| 274 | register "desc" = ""Right Type-C Port"" |
| 275 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 276 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 277 | device usb 3.1 on end |
| 278 | end |
| 279 | chip drivers/usb/acpi |
| 280 | register "desc" = ""Left Type-A Port"" |
| 281 | register "type" = "UPC_TYPE_USB3_A" |
| 282 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 283 | device usb 3.2 on end |
| 284 | end |
| 285 | chip drivers/usb/acpi |
| 286 | register "desc" = ""Right Type-A Port"" |
| 287 | register "type" = "UPC_TYPE_USB3_A" |
| 288 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 289 | device usb 3.3 on end |
| 290 | end |
| 291 | end |
| 292 | end |
| 293 | end |
Furquan Shaikh | 24ec79c | 2020-07-16 13:40:28 -0700 | [diff] [blame] | 294 | device pci 0.5 on |
| 295 | chip drivers/amd/i2s_machine_dev |
| 296 | register "hid" = ""AMDI5682"" |
| 297 | # DMIC select GPIO for ACP machine device |
| 298 | # This GPIO is used to select DMIC0 or DMIC1 by the |
| 299 | # kernel driver. It does not really have a polarity |
| 300 | # since low and high control the selection of DMIC and |
| 301 | # hence does not have an active polarity. |
| 302 | # Kernel driver does not use the polarity field and |
| 303 | # instead treats the GPIO selection as follows: |
| 304 | # Set low (0) = Select DMIC0 |
| 305 | # Set high (1) = Select DMIC1 |
| 306 | register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" |
| 307 | device generic 0.0 on end |
| 308 | end |
| 309 | end # Audio |
Felix Held | 90ca7f4 | 2020-08-21 16:17:05 +0200 | [diff] [blame] | 310 | device pci 0.6 off end # HDA |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 311 | device pci 0.7 on end # non-Sensor Fusion Hub device |
| 312 | end |
Matt Papageorge | 48b2b2b | 2020-07-30 15:32:34 -0500 | [diff] [blame] | 313 | device pci 8.2 off # Internal GPP Bridge 0 to Bus B |
| 314 | device pci 0.0 off end # AHCI |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 315 | end |
| 316 | device pci 14.0 on end # SM |
| 317 | device pci 14.3 on # - D14F3 bridge |
| 318 | chip ec/google/chromeec |
| 319 | device pnp 0c09.0 on |
| 320 | chip ec/google/chromeec/i2c_tunnel |
| 321 | register "uid" = "1" |
| 322 | register "remote_bus" = "8" |
| 323 | device generic 0.0 on |
| 324 | chip drivers/i2c/generic |
| 325 | register "hid" = ""10EC5682"" |
| 326 | register "name" = ""RT58"" |
| 327 | register "uid" = "1" |
| 328 | register "desc" = ""Realtek RT5682"" |
Josie Nordrum | cc72e15 | 2020-08-03 11:39:41 -0600 | [diff] [blame] | 329 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" |
Akshu Agrawal | c7d6d7a | 2020-07-06 19:39:51 +0530 | [diff] [blame] | 330 | register "property_count" = "2" |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 331 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 332 | register "property_list[0].name" = ""realtek,jd-src"" |
| 333 | register "property_list[0].integer" = "1" |
Akshu Agrawal | c7d6d7a | 2020-07-06 19:39:51 +0530 | [diff] [blame] | 334 | register "property_list[1].type" = "ACPI_DP_TYPE_STRING" |
| 335 | register "property_list[1].name" = ""realtek,mclk-name"" |
| 336 | register "property_list[1].string" = ""oscout1"" |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 337 | device i2c 1a on end |
| 338 | end |
| 339 | end |
| 340 | end |
| 341 | chip ec/google/chromeec/i2c_tunnel |
| 342 | register "name" = ""MSTH"" |
| 343 | register "uid" = "1" |
| 344 | register "remote_bus" = "9" |
| 345 | device generic 1.0 on end |
| 346 | end |
Furquan Shaikh | e284bff | 2020-07-02 16:03:06 -0700 | [diff] [blame] | 347 | chip ec/google/chromeec/audio_codec |
| 348 | register "uid" = "1" |
| 349 | device generic 0 on end |
| 350 | end |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 351 | end |
| 352 | end |
| 353 | end |
| 354 | device pci 18.0 on end # Data fabric [0-7] |
| 355 | device pci 18.1 on end |
| 356 | device pci 18.2 on end |
| 357 | device pci 18.3 on end |
| 358 | device pci 18.4 on end |
| 359 | device pci 18.5 on end |
| 360 | device pci 18.6 on end |
| 361 | end # domain |
| 362 | |
| 363 | chip drivers/generic/max98357a |
Raul E Rangel | 19704cd | 2020-06-02 10:43:20 -0600 | [diff] [blame] | 364 | register "hid" = ""MX98357A"" |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 365 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" |
| 366 | register "sdmode_delay" = "5" |
| 367 | device generic 0.1 on end |
| 368 | end |
| 369 | |
| 370 | device mmio 0xfedc5000 on |
| 371 | chip drivers/i2c/tpm |
| 372 | register "hid" = ""GOOG0005"" |
| 373 | register "desc" = ""Cr50 TPM"" |
| 374 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" |
| 375 | device i2c 50 on end |
| 376 | end |
| 377 | end |
| 378 | |
Raul E Rangel | 5e29c0e | 2020-06-12 11:41:16 -0600 | [diff] [blame] | 379 | device mmio 0xfedca000 off end # UART1 |
| 380 | device mmio 0xfedce000 off end # UART2 |
| 381 | device mmio 0xfedcf000 off end # UART3 |
| 382 | |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 383 | end # chip soc/amd/picasso |