Elyes HAOUAS | f7b2fe6 | 2020-05-07 12:38:15 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-or-later |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 2 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 3 | source "src/soc/intel/xeon_sp/skx/Kconfig" |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 4 | source "src/soc/intel/xeon_sp/cpx/Kconfig" |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 5 | |
| 6 | config XEON_SP_COMMON_BASE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 7 | bool |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 8 | |
| 9 | config SOC_INTEL_SKYLAKE_SP |
| 10 | bool |
| 11 | select XEON_SP_COMMON_BASE |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 12 | select PLATFORM_USES_FSP2_0 |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 13 | help |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 14 | Intel Skylake-SP support |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 15 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 16 | config SOC_INTEL_COOPERLAKE_SP |
| 17 | bool |
| 18 | select XEON_SP_COMMON_BASE |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 19 | select PLATFORM_USES_FSP2_2 |
Elyes HAOUAS | 86ea251 | 2020-08-18 21:12:37 +0200 | [diff] [blame] | 20 | select CACHE_MRC_SETTINGS |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 21 | help |
| 22 | Intel Cooperlake-SP support |
| 23 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 24 | if XEON_SP_COMMON_BASE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 25 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 26 | config CPU_SPECIFIC_OPTIONS |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 27 | def_bool y |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 28 | select ARCH_ALL_STAGES_X86_32 |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 29 | select BOOT_DEVICE_SUPPORTS_WRITES |
Angel Pons | eeb4705 | 2020-09-02 15:29:49 +0200 | [diff] [blame] | 30 | select CPU_INTEL_COMMON |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 31 | select SOC_INTEL_COMMON |
| 32 | select SOC_INTEL_COMMON_RESET |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 33 | select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
| 34 | select FSP_T_XIP |
| 35 | select FSP_M_XIP |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 36 | select POSTCAR_STAGE |
| 37 | select IOAPIC |
| 38 | select PARALLEL_MP |
Kyösti Mälkki | c3c5521 | 2020-06-17 10:34:26 +0300 | [diff] [blame] | 39 | select ACPI_NO_SMI_GNVS |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 40 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK |
| 42 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 43 | select SOC_INTEL_COMMON_BLOCK_TIMER |
| 44 | select SOC_INTEL_COMMON_BLOCK_LPC |
| 45 | select SOC_INTEL_COMMON_BLOCK_RTC |
| 46 | select SOC_INTEL_COMMON_BLOCK_SPI |
| 47 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Maxim Polyakov | 5b06ffe | 2020-03-22 14:57:36 +0300 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_GPIO |
| 49 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Maxim Polyakov | 5b06ffe | 2020-03-22 14:57:36 +0300 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_PCR |
Arthur Heymans | 695dd29 | 2020-11-12 21:05:09 +0100 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_P2SB |
Arthur Heymans | f4f332d | 2020-11-19 14:23:46 +0100 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_PMC |
| 54 | select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_SMM |
Arthur Heymans | f472124 | 2020-11-19 16:20:27 +0100 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_TCO |
Marc Jones | 63e2a84 | 2020-12-02 11:33:02 -0700 | [diff] [blame^] | 57 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 58 | select TSC_MONOTONIC_TIMER |
| 59 | select UDELAY_TSC |
| 60 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 61 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 62 | select FSP_CAR |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 63 | select CPU_INTEL_COMMON_SMM |
Arthur Heymans | f4f332d | 2020-11-19 14:23:46 +0100 | [diff] [blame] | 64 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 65 | select SMM_TSEG |
| 66 | select HAVE_SMI_HANDLER |
| 67 | select X86_SMM_LOADER_VERSION2 |
Arthur Heymans | f4f332d | 2020-11-19 14:23:46 +0100 | [diff] [blame] | 68 | select REG_SCRIPT |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 69 | |
| 70 | config MAINBOARD_USES_FSP2_0 |
| 71 | bool |
| 72 | default y |
| 73 | |
| 74 | config USE_FSP2_0_DRIVER |
| 75 | def_bool y |
| 76 | depends on MAINBOARD_USES_FSP2_0 |
| 77 | select PLATFORM_USES_FSP2_0 |
Jonathan Zhang | 951a409 | 2020-06-09 18:01:32 -0700 | [diff] [blame] | 78 | select UDK_202005_BINDING |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 79 | select POSTCAR_STAGE |
| 80 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 81 | config MAX_SOCKET |
| 82 | int |
| 83 | default 2 |
| 84 | |
| 85 | # For 2S config, the number of cpus could be as high as |
| 86 | # 2 threads * 20 cores * 2 sockets |
| 87 | config MAX_CPUS |
| 88 | int |
| 89 | default 80 |
| 90 | |
| 91 | config PCR_BASE_ADDRESS |
| 92 | hex |
| 93 | default 0xfd000000 |
| 94 | help |
| 95 | This option allows you to select MMIO Base Address of sideband bus. |
| 96 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 97 | config DCACHE_BSP_STACK_SIZE |
| 98 | hex |
| 99 | default 0x10000 |
| 100 | |
| 101 | config MMCONF_BASE_ADDRESS |
| 102 | hex |
| 103 | default 0x80000000 |
| 104 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 105 | config C_ENV_BOOTBLOCK_SIZE |
| 106 | hex |
| 107 | default 0xC000 |
| 108 | |
| 109 | config HEAP_SIZE |
| 110 | hex |
| 111 | default 0x80000 |
| 112 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 113 | endif ## SOC_INTEL_XEON_SP |