commit	662da6cf7b181ea2787ba001d9cbb6d41916abec	[log] [tgz]
author	Andrey Petrov <anpetrov@fb.com>	Mon Mar 16 22:46:57 2020 -0700
committer	Andrey Petrov <andrey.petrov@gmail.com>	Thu Mar 26 02:06:45 2020 +0000
tree	63a95b276913110c423c566db78b856650582ad3
parent	a1b15172d7f0303e8a1fe147a778d73d4dc26b1a [diff]

soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/ocp/tiogapass/Kconfig[diff]
src/mainboard/ocp/tiogapass/devicetree.cb[diff]
src/mainboard/ocp/tiogapass/dsdt.asl[diff]
src/soc/intel/xeon_sp/Kconfig[diff]
src/soc/intel/xeon_sp/Makefile.inc[diff]
src/soc/intel/xeon_sp/bootblock.c[Renamed from src/soc/intel/xeon_sp/bootblock/bootblock.c - diff]
src/soc/intel/xeon_sp/include/soc/util.h[Renamed from src/soc/intel/xeon_sp/include/soc/soc_util.h - diff]
src/soc/intel/xeon_sp/lpc.c[diff]
src/soc/intel/xeon_sp/romstage.c[diff]
src/soc/intel/xeon_sp/skx/Kconfig[Added - diff]
src/soc/intel/xeon_sp/skx/Makefile.inc[Added - diff]
src/soc/intel/xeon_sp/skx/acpi.c[Renamed from src/soc/intel/xeon_sp/acpi.c - diff]
src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl[Renamed from src/soc/intel/xeon_sp/acpi/globalnvs.asl - diff]
src/soc/intel/xeon_sp/skx/acpi/iiostack.asl[Renamed from src/soc/intel/xeon_sp/acpi/iiostack.asl - diff]
src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl[Renamed from src/soc/intel/xeon_sp/acpi/pci_irq.asl - diff]
src/soc/intel/xeon_sp/skx/acpi/uncore.asl[Renamed from src/soc/intel/xeon_sp/acpi/uncore.asl - diff]
src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl[Renamed from src/soc/intel/xeon_sp/acpi/uncore_irq.asl - diff]
src/soc/intel/xeon_sp/skx/chip.c[Renamed from src/soc/intel/xeon_sp/chip.c - diff]
src/soc/intel/xeon_sp/skx/chip.h[Renamed from src/soc/intel/xeon_sp/chip.h - diff]
src/soc/intel/xeon_sp/skx/cpu.c[Renamed from src/soc/intel/xeon_sp/cpu.c - diff]
src/soc/intel/xeon_sp/skx/hob_display.c[Renamed from src/soc/intel/xeon_sp/hob_display.c - diff]
src/soc/intel/xeon_sp/skx/include/soc/acpi.h[Renamed from src/soc/intel/xeon_sp/include/soc/acpi.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/cpu.h[Renamed from src/soc/intel/xeon_sp/include/soc/cpu.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h[Renamed from src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/irq.h[Renamed from src/soc/intel/xeon_sp/include/soc/irq.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/msr.h[Renamed from src/soc/intel/xeon_sp/include/soc/msr.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/nvs.h[Renamed from src/soc/intel/xeon_sp/include/soc/nvs.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h[Renamed from src/soc/intel/xeon_sp/include/soc/pci_devs.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/ramstage.h[Renamed from src/soc/intel/xeon_sp/include/soc/ramstage.h - diff]
src/soc/intel/xeon_sp/skx/include/soc/soc_util.h[Added - diff]
src/soc/intel/xeon_sp/skx/romstage.c[Added - diff]
src/soc/intel/xeon_sp/skx/soc_util.c[Renamed from src/soc/intel/xeon_sp/soc_util.c - diff]
src/soc/intel/xeon_sp/skx/upd_display.c[Renamed from src/soc/intel/xeon_sp/upd_display.c - diff]
src/soc/intel/xeon_sp/uncore.c[diff]
src/soc/intel/xeon_sp/util.c[Added - diff]

35 files changed

tree: 63a95b276913110c423c566db78b856650582ad3

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

https://www.coreboot.org/Supported_Motherboards

Build Requirements

make
gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
iasl (for targets with ACPI support)
pkg-config
libssl-dev (openssl)

Optional:

doxygen (for generating/viewing documentation)
gdb (for better debugging facilities on some targets)
ncurses (for make menuconfig and make nconfig)
flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.