soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2
CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues
to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0.
Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE,
and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding
StackBase and StackSize FSP-M UPD parameters is removed.
Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable()
to indicate that FSP-S multi phase init is not enabled, since it is
not supported by CPX-SP FSP.
TESTED=booted YV3 config A to target OS.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index b410dec..cf9ba94 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -9,12 +9,14 @@
config SOC_INTEL_SKYLAKE_SP
bool
select XEON_SP_COMMON_BASE
+ select PLATFORM_USES_FSP2_0
help
Intel Skylake-SP support
config SOC_INTEL_COOPERLAKE_SP
bool
select XEON_SP_COMMON_BASE
+ select PLATFORM_USES_FSP2_2
help
Intel Cooperlake-SP support
@@ -31,7 +33,6 @@
select POSTCAR_CONSOLE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
- select PLATFORM_USES_FSP2_0
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select FSP_T_XIP
select FSP_M_XIP