Elyes HAOUAS | f7b2fe6 | 2020-05-07 12:38:15 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-or-later |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 2 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 3 | source "src/soc/intel/xeon_sp/skx/Kconfig" |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 4 | source "src/soc/intel/xeon_sp/cpx/Kconfig" |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 5 | |
| 6 | config XEON_SP_COMMON_BASE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 7 | bool |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 8 | |
| 9 | config SOC_INTEL_SKYLAKE_SP |
| 10 | bool |
| 11 | select XEON_SP_COMMON_BASE |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame^] | 12 | select PLATFORM_USES_FSP2_0 |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 13 | help |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 14 | Intel Skylake-SP support |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 15 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 16 | config SOC_INTEL_COOPERLAKE_SP |
| 17 | bool |
| 18 | select XEON_SP_COMMON_BASE |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame^] | 19 | select PLATFORM_USES_FSP2_2 |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 20 | help |
| 21 | Intel Cooperlake-SP support |
| 22 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 23 | if XEON_SP_COMMON_BASE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 24 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 25 | config CPU_SPECIFIC_OPTIONS |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 26 | def_bool y |
| 27 | select ARCH_BOOTBLOCK_X86_32 |
| 28 | select ARCH_RAMSTAGE_X86_32 |
| 29 | select ARCH_ROMSTAGE_X86_32 |
| 30 | select ARCH_VERSTAGE_X86_32 |
| 31 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 32 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 33 | select POSTCAR_CONSOLE |
| 34 | select SOC_INTEL_COMMON |
| 35 | select SOC_INTEL_COMMON_RESET |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 36 | select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
| 37 | select FSP_T_XIP |
| 38 | select FSP_M_XIP |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 39 | select POSTCAR_STAGE |
| 40 | select IOAPIC |
| 41 | select PARALLEL_MP |
Kyösti Mälkki | c3c5521 | 2020-06-17 10:34:26 +0300 | [diff] [blame] | 42 | select ACPI_NO_SMI_GNVS |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 43 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK |
| 45 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 46 | select SOC_INTEL_COMMON_BLOCK_TIMER |
| 47 | select SOC_INTEL_COMMON_BLOCK_LPC |
| 48 | select SOC_INTEL_COMMON_BLOCK_RTC |
| 49 | select SOC_INTEL_COMMON_BLOCK_SPI |
| 50 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Maxim Polyakov | 5b06ffe | 2020-03-22 14:57:36 +0300 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_GPIO |
| 52 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| 53 | select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS |
| 54 | select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_PCR |
| 56 | select TSC_MONOTONIC_TIMER |
| 57 | select UDELAY_TSC |
| 58 | select SUPPORT_CPU_UCODE_IN_CBFS |
Nico Huber | 0266be0 | 2020-03-08 18:36:00 +0100 | [diff] [blame] | 59 | select MICROCODE_BLOB_NOT_HOOKED_UP |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 60 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 61 | select FSP_CAR |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 62 | |
| 63 | config MAINBOARD_USES_FSP2_0 |
| 64 | bool |
| 65 | default y |
| 66 | |
| 67 | config USE_FSP2_0_DRIVER |
| 68 | def_bool y |
| 69 | depends on MAINBOARD_USES_FSP2_0 |
| 70 | select PLATFORM_USES_FSP2_0 |
Jonathan Zhang | 951a409 | 2020-06-09 18:01:32 -0700 | [diff] [blame] | 71 | select UDK_202005_BINDING |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 72 | select POSTCAR_CONSOLE |
| 73 | select POSTCAR_STAGE |
| 74 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 75 | config MAX_SOCKET |
| 76 | int |
| 77 | default 2 |
| 78 | |
| 79 | # For 2S config, the number of cpus could be as high as |
| 80 | # 2 threads * 20 cores * 2 sockets |
| 81 | config MAX_CPUS |
| 82 | int |
| 83 | default 80 |
| 84 | |
| 85 | config PCR_BASE_ADDRESS |
| 86 | hex |
| 87 | default 0xfd000000 |
| 88 | help |
| 89 | This option allows you to select MMIO Base Address of sideband bus. |
| 90 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 91 | config DCACHE_BSP_STACK_SIZE |
| 92 | hex |
| 93 | default 0x10000 |
| 94 | |
| 95 | config MMCONF_BASE_ADDRESS |
| 96 | hex |
| 97 | default 0x80000000 |
| 98 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 99 | config C_ENV_BOOTBLOCK_SIZE |
| 100 | hex |
| 101 | default 0xC000 |
| 102 | |
| 103 | config HEAP_SIZE |
| 104 | hex |
| 105 | default 0x80000 |
| 106 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 107 | endif ## SOC_INTEL_XEON_SP |