Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 17 | #include <cbmem.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 18 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 23 | #include <boot/tables.h> |
| 24 | #include <arch/acpi.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 25 | #include <northbridge/intel/pineview/pineview.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 26 | #include <cpu/intel/smm_reloc.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 27 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 28 | /* Reserve everything between A segment and 1MB: |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 29 | * |
| 30 | * 0xa0000 - 0xbffff: legacy VGA |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 31 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 32 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 33 | */ |
| 34 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 35 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 36 | static void add_fixed_resources(struct device *dev, int index) |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 37 | { |
| 38 | struct resource *resource; |
| 39 | |
| 40 | resource = new_resource(dev, index++); |
| 41 | resource->base = (resource_t) 0xfed00000; |
| 42 | resource->size = (resource_t) 0x00100000; |
| 43 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 44 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 45 | |
| 46 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 47 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 48 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 49 | (0x100000 - 0xc0000) >> 10); |
| 50 | } |
| 51 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 52 | static void mch_domain_read_resources(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 53 | { |
| 54 | u64 tom, touud; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 55 | u32 tomk, tolud, tseg_sizek; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 56 | u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 57 | u16 index; |
| 58 | const u32 top32memk = 4 * (GiB / KiB); |
| 59 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 60 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 61 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 62 | index = 3; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 63 | |
| 64 | pci_domain_read_resources(dev); |
| 65 | |
| 66 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 67 | touud = pci_read_config16(mch, TOUUD); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 68 | touud <<= 20; |
| 69 | |
| 70 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 71 | tolud = pci_read_config16(mch, TOLUD) & 0xfff0; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 72 | tolud <<= 16; |
| 73 | |
| 74 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 75 | tom = pci_read_config16(mch, TOM) & 0x1ff; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 76 | tom <<= 27; |
| 77 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 78 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 79 | touud, tolud, tom); |
| 80 | |
| 81 | tomk = tolud >> 10; |
| 82 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 83 | /* Graphics memory */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 84 | const u16 ggc = pci_read_config16(mch, GGC); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 85 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 86 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
| 87 | tomk -= gms_sizek; |
| 88 | |
| 89 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 90 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 91 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
| 92 | tomk -= gsm_sizek; |
| 93 | |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 94 | const u32 tseg_basek = pci_read_config32(mch, TSEG) >> 10; |
| 95 | const u32 igd_basek = pci_read_config32(mch, GBSM) >> 10; |
| 96 | const u32 gtt_basek = pci_read_config32(mch, BGSM) >> 10; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 97 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 98 | /* Subtract TSEG size */ |
| 99 | tseg_sizek = gtt_basek - tseg_basek; |
| 100 | tomk -= tseg_sizek; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 101 | printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); |
| 102 | |
| 103 | /* cbmem_top can be shifted downwards due to alignment. |
| 104 | Mark the region between cbmem_top and tomk as unusable */ |
| 105 | cbmem_topk = (uint32_t)cbmem_top() >> 10; |
| 106 | delta_cbmem = tomk - cbmem_topk; |
| 107 | tomk -= delta_cbmem; |
| 108 | |
| 109 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", |
| 110 | delta_cbmem); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 111 | |
| 112 | /* Report the memory regions */ |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 113 | ram_resource(dev, index++, 0, 640); |
| 114 | ram_resource(dev, index++, 768, tomk - 768); |
| 115 | reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); |
| 116 | reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); |
| 117 | reserved_ram_resource(dev, index++, igd_basek, gms_sizek); |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 118 | reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 119 | |
| 120 | /* |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 121 | * If > 4GB installed then memory from TOLUD to 4GB |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 122 | * is remapped above TOM, TOUUD will account for both |
| 123 | */ |
| 124 | touud >>= 10; /* Convert to KB */ |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 125 | if (touud > top32memk) { |
| 126 | ram_resource(dev, index++, top32memk, touud - top32memk); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 127 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 128 | (touud - top32memk) >> 10); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 129 | } |
| 130 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 131 | if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { |
| 132 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 133 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 134 | fixed_mem_resource(dev, index++, pcie_config_base >> 10, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 135 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 136 | } |
| 137 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 138 | add_fixed_resources(dev, index); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 139 | } |
| 140 | |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 141 | void northbridge_write_smram(u8 smram) |
| 142 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 143 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 144 | |
| 145 | if (dev == NULL) |
| 146 | die("could not find pci 00:00.0!\n"); |
| 147 | |
| 148 | pci_write_config8(dev, SMRAM, smram); |
| 149 | } |
| 150 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 151 | static void mch_domain_set_resources(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 152 | { |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 153 | struct resource *res; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 154 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 155 | for (res = dev->resource_list; res; res = res->next) |
| 156 | report_resource_stored(dev, res, ""); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 157 | |
| 158 | assign_resources(dev->link_list); |
| 159 | } |
| 160 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 161 | static void mch_domain_init(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 162 | { |
| 163 | u32 reg32; |
| 164 | |
| 165 | /* Enable SERR */ |
| 166 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 167 | reg32 |= PCI_COMMAND_SERR; |
| 168 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 169 | } |
| 170 | |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 171 | static const char *northbridge_acpi_name(const struct device *dev) |
| 172 | { |
| 173 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 174 | return "PCI0"; |
| 175 | |
| 176 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 177 | return NULL; |
| 178 | |
| 179 | switch (dev->path.pci.devfn) { |
| 180 | case PCI_DEVFN(0, 0): |
| 181 | return "MCHC"; |
| 182 | } |
| 183 | |
| 184 | return NULL; |
| 185 | } |
| 186 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 187 | static struct device_operations pci_domain_ops = { |
| 188 | .read_resources = mch_domain_read_resources, |
| 189 | .set_resources = mch_domain_set_resources, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 190 | .init = mch_domain_init, |
| 191 | .scan_bus = pci_domain_scan_bus, |
Arthur Heymans | 3b633bb | 2017-04-28 22:36:17 +0200 | [diff] [blame] | 192 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 193 | .acpi_name = northbridge_acpi_name, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 194 | }; |
| 195 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 196 | static struct device_operations cpu_bus_ops = { |
| 197 | .read_resources = DEVICE_NOOP, |
| 198 | .set_resources = DEVICE_NOOP, |
| 199 | .enable_resources = DEVICE_NOOP, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 200 | .init = mp_cpu_bus_init, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 201 | }; |
| 202 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 203 | static void enable_dev(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 204 | { |
| 205 | /* Set the operations if it is a special bus type */ |
| 206 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 207 | dev->ops = &pci_domain_ops; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 208 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 209 | dev->ops = &cpu_bus_ops; |
| 210 | } |
| 211 | } |
| 212 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 213 | struct chip_operations northbridge_intel_pineview_ops = { |
| 214 | CHIP_NAME("Intel Pineview Northbridge") |
| 215 | .enable_dev = enable_dev, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 216 | }; |