Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 17 | #include <cbmem.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 18 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 23 | #include <stdlib.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 24 | #include <cpu/cpu.h> |
| 25 | #include <boot/tables.h> |
| 26 | #include <arch/acpi.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 27 | #include <northbridge/intel/pineview/pineview.h> |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 28 | #include <cpu/intel/smm/gen1/smi.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 29 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 30 | /* Reserve everything between A segment and 1MB: |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 31 | * |
| 32 | * 0xa0000 - 0xbffff: legacy VGA |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 33 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 34 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 35 | */ |
| 36 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 37 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 38 | static void add_fixed_resources(struct device *dev, int index) |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 39 | { |
| 40 | struct resource *resource; |
| 41 | |
| 42 | resource = new_resource(dev, index++); |
| 43 | resource->base = (resource_t) 0xfed00000; |
| 44 | resource->size = (resource_t) 0x00100000; |
| 45 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 46 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 47 | |
| 48 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 49 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 50 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 51 | (0x100000 - 0xc0000) >> 10); |
| 52 | } |
| 53 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 54 | static void mch_domain_read_resources(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 55 | { |
| 56 | u64 tom, touud; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 57 | u32 tomk, tolud, tseg_sizek; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 58 | u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 59 | u16 index; |
| 60 | const u32 top32memk = 4 * (GiB / KiB); |
| 61 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 62 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 63 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 64 | index = 3; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 65 | |
| 66 | pci_domain_read_resources(dev); |
| 67 | |
| 68 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 69 | touud = pci_read_config16(mch, TOUUD); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 70 | touud <<= 20; |
| 71 | |
| 72 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 73 | tolud = pci_read_config16(mch, TOLUD) & 0xfff0; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 74 | tolud <<= 16; |
| 75 | |
| 76 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 77 | tom = pci_read_config16(mch, TOM) & 0x1ff; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 78 | tom <<= 27; |
| 79 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 80 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 81 | touud, tolud, tom); |
| 82 | |
| 83 | tomk = tolud >> 10; |
| 84 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 85 | /* Graphics memory */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 86 | const u16 ggc = pci_read_config16(mch, GGC); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 87 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 88 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
| 89 | tomk -= gms_sizek; |
| 90 | |
| 91 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 92 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 93 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
| 94 | tomk -= gsm_sizek; |
| 95 | |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 96 | const u32 tseg_basek = pci_read_config32(mch, TSEG) >> 10; |
| 97 | const u32 igd_basek = pci_read_config32(mch, GBSM) >> 10; |
| 98 | const u32 gtt_basek = pci_read_config32(mch, BGSM) >> 10; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 99 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 100 | /* Subtract TSEG size */ |
| 101 | tseg_sizek = gtt_basek - tseg_basek; |
| 102 | tomk -= tseg_sizek; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 103 | printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); |
| 104 | |
| 105 | /* cbmem_top can be shifted downwards due to alignment. |
| 106 | Mark the region between cbmem_top and tomk as unusable */ |
| 107 | cbmem_topk = (uint32_t)cbmem_top() >> 10; |
| 108 | delta_cbmem = tomk - cbmem_topk; |
| 109 | tomk -= delta_cbmem; |
| 110 | |
| 111 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", |
| 112 | delta_cbmem); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 113 | |
| 114 | /* Report the memory regions */ |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 115 | ram_resource(dev, index++, 0, 640); |
| 116 | ram_resource(dev, index++, 768, tomk - 768); |
| 117 | reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); |
| 118 | reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); |
| 119 | reserved_ram_resource(dev, index++, igd_basek, gms_sizek); |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 120 | reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 121 | |
| 122 | /* |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 123 | * If > 4GB installed then memory from TOLUD to 4GB |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 124 | * is remapped above TOM, TOUUD will account for both |
| 125 | */ |
| 126 | touud >>= 10; /* Convert to KB */ |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 127 | if (touud > top32memk) { |
| 128 | ram_resource(dev, index++, top32memk, touud - top32memk); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 129 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 130 | (touud - top32memk) >> 10); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 131 | } |
| 132 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 133 | if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { |
| 134 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 135 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 136 | fixed_mem_resource(dev, index++, pcie_config_base >> 10, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 137 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 138 | } |
| 139 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 140 | add_fixed_resources(dev, index); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 141 | } |
| 142 | |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 143 | void northbridge_write_smram(u8 smram) |
| 144 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 145 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 146 | |
| 147 | if (dev == NULL) |
| 148 | die("could not find pci 00:00.0!\n"); |
| 149 | |
| 150 | pci_write_config8(dev, SMRAM, smram); |
| 151 | } |
| 152 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 153 | static void mch_domain_set_resources(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 154 | { |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 155 | struct resource *res; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 156 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 157 | for (res = dev->resource_list; res; res = res->next) |
| 158 | report_resource_stored(dev, res, ""); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 159 | |
| 160 | assign_resources(dev->link_list); |
| 161 | } |
| 162 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 163 | static void mch_domain_init(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 164 | { |
| 165 | u32 reg32; |
| 166 | |
| 167 | /* Enable SERR */ |
| 168 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 169 | reg32 |= PCI_COMMAND_SERR; |
| 170 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 171 | } |
| 172 | |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 173 | static const char *northbridge_acpi_name(const struct device *dev) |
| 174 | { |
| 175 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 176 | return "PCI0"; |
| 177 | |
| 178 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 179 | return NULL; |
| 180 | |
| 181 | switch (dev->path.pci.devfn) { |
| 182 | case PCI_DEVFN(0, 0): |
| 183 | return "MCHC"; |
| 184 | } |
| 185 | |
| 186 | return NULL; |
| 187 | } |
| 188 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 189 | static struct device_operations pci_domain_ops = { |
| 190 | .read_resources = mch_domain_read_resources, |
| 191 | .set_resources = mch_domain_set_resources, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 192 | .init = mch_domain_init, |
| 193 | .scan_bus = pci_domain_scan_bus, |
Arthur Heymans | 3b633bb | 2017-04-28 22:36:17 +0200 | [diff] [blame] | 194 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 195 | .acpi_name = northbridge_acpi_name, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 196 | }; |
| 197 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 198 | static struct device_operations cpu_bus_ops = { |
| 199 | .read_resources = DEVICE_NOOP, |
| 200 | .set_resources = DEVICE_NOOP, |
| 201 | .enable_resources = DEVICE_NOOP, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame^] | 202 | .init = mp_cpu_bus_init, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 203 | }; |
| 204 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 205 | static void enable_dev(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 206 | { |
| 207 | /* Set the operations if it is a special bus type */ |
| 208 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 209 | dev->ops = &pci_domain_ops; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 210 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 211 | dev->ops = &cpu_bus_ops; |
| 212 | } |
| 213 | } |
| 214 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 215 | struct chip_operations northbridge_intel_pineview_ops = { |
| 216 | CHIP_NAME("Intel Pineview Northbridge") |
| 217 | .enable_dev = enable_dev, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 218 | }; |