V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 6 | |
| 7 | # FSP Configuration |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 8 | register "ScsEmmcHs400Enabled" = "0" |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 9 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 10 | # VR Settings Configuration for 5 Domains |
| 11 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 12 | #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | |
| 13 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 14 | #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | |
| 15 | #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | |
| 16 | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | |
| 17 | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | |
| 18 | #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | |
| 19 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | |
| 20 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 21 | #| IccMax | Auto | Auto | Auto | Auto | Auto | |
| 22 | #| VrVoltageLimit*| 0 | 0 | 0 | 0 | 0 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 23 | #+----------------+-------+-------+-------------+-------------+-------+ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 24 | #* VrVoltageLimit command not sent. |
| 25 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 26 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 27 | .vr_config_enable = 1, |
| 28 | .psi1threshold = VR_CFG_AMP(20), |
| 29 | .psi2threshold = VR_CFG_AMP(4), |
| 30 | .psi3threshold = VR_CFG_AMP(1), |
| 31 | .psi3enable = 1, |
| 32 | .psi4enable = 1, |
| 33 | .imon_slope = 0, |
| 34 | .imon_offset = 0, |
| 35 | .icc_max = 0, |
| 36 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 37 | }" |
| 38 | |
| 39 | register "domain_vr_config[VR_IA_CORE]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 40 | .vr_config_enable = 1, |
| 41 | .psi1threshold = VR_CFG_AMP(20), |
| 42 | .psi2threshold = VR_CFG_AMP(5), |
| 43 | .psi3threshold = VR_CFG_AMP(1), |
| 44 | .psi3enable = 1, |
| 45 | .psi4enable = 1, |
| 46 | .imon_slope = 0, |
| 47 | .imon_offset = 0, |
| 48 | .icc_max = 0, |
| 49 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 50 | }" |
| 51 | |
| 52 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 53 | .vr_config_enable = 1, |
| 54 | .psi1threshold = VR_CFG_AMP(20), |
| 55 | .psi2threshold = VR_CFG_AMP(5), |
| 56 | .psi3threshold = VR_CFG_AMP(1), |
| 57 | .psi3enable = 1, |
| 58 | .psi4enable = 1, |
| 59 | .imon_slope = 0, |
| 60 | .imon_offset = 0, |
| 61 | .icc_max = 0, |
| 62 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 63 | }" |
| 64 | |
| 65 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 66 | .vr_config_enable = 1, |
| 67 | .psi1threshold = VR_CFG_AMP(20), |
| 68 | .psi2threshold = VR_CFG_AMP(5), |
| 69 | .psi3threshold = VR_CFG_AMP(1), |
| 70 | .psi3enable = 1, |
| 71 | .psi4enable = 1, |
| 72 | .imon_slope = 0, |
| 73 | .imon_offset = 0, |
| 74 | .icc_max = 0, |
| 75 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 76 | }" |
| 77 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 78 | # Enable Root port. |
| 79 | register "PcieRpEnable[3]" = "1" |
| 80 | register "PcieRpEnable[4]" = "1" |
| 81 | register "PcieRpEnable[8]" = "1" |
| 82 | register "PcieRpEnable[16]" = "1" |
| 83 | |
| 84 | # Enable CLKREQ# |
| 85 | register "PcieRpClkReqSupport[3]" = "1" |
| 86 | register "PcieRpClkReqSupport[4]" = "1" |
| 87 | register "PcieRpClkReqSupport[8]" = "1" |
| 88 | register "PcieRpClkReqSupport[16]" = "1" |
| 89 | |
| 90 | # SRCCLKREQ# |
| 91 | register "PcieRpClkReqNumber[3]" = "2" |
| 92 | register "PcieRpClkReqNumber[4]" = "1" |
| 93 | register "PcieRpClkReqNumber[8]" = "6" |
| 94 | register "PcieRpClkReqNumber[16]" = "7" |
| 95 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 96 | |
| 97 | register "SsicPortEnable" = "1" # Enable SSIC for WWAN |
| 98 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 99 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 100 | register "SerialIoDevMode" = "{ |
| 101 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 102 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 103 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 104 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 105 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 106 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 107 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 108 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 109 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 110 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 111 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 112 | }" |
| 113 | |
| 114 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 115 | register "power_limits_config" = "{ |
| 116 | .tdp_pl2_override = 25, |
| 117 | }" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 118 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 119 | device domain 0 on |
Felix Singer | 6c83a71 | 2024-06-23 00:25:18 +0200 | [diff] [blame] | 120 | device ref south_xhci on |
| 121 | register "usb2_ports" = "{ |
| 122 | [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ |
| 123 | [1] = USB2_PORT_MAX(OC5), /* Front panel */ |
| 124 | [2] = USB2_PORT_MAX(OC4), /* Back panel */ |
| 125 | [3] = USB2_PORT_MAX(OC4), /* Back panel */ |
| 126 | [4] = USB2_PORT_MAX(OC1), /* Back panel-1 */ |
| 127 | [5] = USB2_PORT_MAX(OC1), /* Back panel */ |
| 128 | [6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ |
| 129 | [7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */ |
| 130 | [8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */ |
| 131 | [9] = USB2_PORT_MAX(OC2), /* Front panel */ |
| 132 | [10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ |
| 133 | [11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */ |
| 134 | [12] = USB2_PORT_MAX(OC3), /* Back panel */ |
| 135 | [13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ |
| 136 | }" |
| 137 | |
| 138 | register "usb3_ports" = "{ |
| 139 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */ |
| 140 | [1] = USB3_PORT_DEFAULT(OC1), /* Back panel */ |
| 141 | [2] = USB3_PORT_DEFAULT(OC1), /* Back panel */ |
| 142 | [3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */ |
| 143 | [4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ |
| 144 | [5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */ |
| 145 | [6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ |
| 146 | [7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ |
| 147 | [8] = USB3_PORT_DEFAULT(OC3), /* Back panel */ |
| 148 | [9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */ |
| 149 | }" |
| 150 | end |
Felix Singer | 2dff4f0 | 2023-11-16 01:17:31 +0100 | [diff] [blame] | 151 | device ref i2c2 off end |
| 152 | device ref i2c3 off end |
Felix Singer | df7de39 | 2024-06-23 04:59:03 +0200 | [diff] [blame] | 153 | device ref sata on |
| 154 | register "SataSalpSupport" = "1" |
| 155 | register "SataPortsEnable" = "{ |
| 156 | [0] = 1, |
| 157 | [1] = 1, |
| 158 | [2] = 1, |
| 159 | [3] = 1, |
| 160 | [4] = 1, |
| 161 | [5] = 1, |
| 162 | [6] = 1, |
| 163 | [7] = 1, |
| 164 | }" |
| 165 | end |
Felix Singer | 2dff4f0 | 2023-11-16 01:17:31 +0100 | [diff] [blame] | 166 | device ref i2c4 off end |
| 167 | device ref pcie_rp1 off end |
| 168 | device ref pcie_rp3 on end |
| 169 | device ref pcie_rp4 on end |
| 170 | device ref pcie_rp5 on end |
| 171 | device ref emmc off end |
| 172 | device ref sdxc off end |
| 173 | device ref lpc_espi on |
Felix Singer | 4b72203 | 2024-06-23 20:32:15 +0200 | [diff] [blame^] | 174 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 175 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 176 | #chip drivers/pc80/tpm |
| 177 | # device pnp 0c31.0 on end |
| 178 | #end |
Felix Singer | 2dff4f0 | 2023-11-16 01:17:31 +0100 | [diff] [blame] | 179 | end |
| 180 | device ref gbe on end |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 181 | end |
| 182 | end |