V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 6 | |
| 7 | # FSP Configuration |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 8 | register "ScsEmmcHs400Enabled" = "0" |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 9 | |
| 10 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 11 | |
| 12 | # VR Settings Configuration for 5 Domains |
| 13 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 14 | #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | |
| 15 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 16 | #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | |
| 17 | #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | |
| 18 | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | |
| 19 | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | |
| 20 | #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | |
| 21 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | |
| 22 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 23 | #| IccMax | Auto | Auto | Auto | Auto | Auto | |
| 24 | #| VrVoltageLimit*| 0 | 0 | 0 | 0 | 0 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 25 | #+----------------+-------+-------+-------------+-------------+-------+ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 26 | #* VrVoltageLimit command not sent. |
| 27 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 28 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 29 | .vr_config_enable = 1, |
| 30 | .psi1threshold = VR_CFG_AMP(20), |
| 31 | .psi2threshold = VR_CFG_AMP(4), |
| 32 | .psi3threshold = VR_CFG_AMP(1), |
| 33 | .psi3enable = 1, |
| 34 | .psi4enable = 1, |
| 35 | .imon_slope = 0, |
| 36 | .imon_offset = 0, |
| 37 | .icc_max = 0, |
| 38 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 39 | }" |
| 40 | |
| 41 | register "domain_vr_config[VR_IA_CORE]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 42 | .vr_config_enable = 1, |
| 43 | .psi1threshold = VR_CFG_AMP(20), |
| 44 | .psi2threshold = VR_CFG_AMP(5), |
| 45 | .psi3threshold = VR_CFG_AMP(1), |
| 46 | .psi3enable = 1, |
| 47 | .psi4enable = 1, |
| 48 | .imon_slope = 0, |
| 49 | .imon_offset = 0, |
| 50 | .icc_max = 0, |
| 51 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 52 | }" |
| 53 | |
| 54 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 55 | .vr_config_enable = 1, |
| 56 | .psi1threshold = VR_CFG_AMP(20), |
| 57 | .psi2threshold = VR_CFG_AMP(5), |
| 58 | .psi3threshold = VR_CFG_AMP(1), |
| 59 | .psi3enable = 1, |
| 60 | .psi4enable = 1, |
| 61 | .imon_slope = 0, |
| 62 | .imon_offset = 0, |
| 63 | .icc_max = 0, |
| 64 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 65 | }" |
| 66 | |
| 67 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 68 | .vr_config_enable = 1, |
| 69 | .psi1threshold = VR_CFG_AMP(20), |
| 70 | .psi2threshold = VR_CFG_AMP(5), |
| 71 | .psi3threshold = VR_CFG_AMP(1), |
| 72 | .psi3enable = 1, |
| 73 | .psi4enable = 1, |
| 74 | .imon_slope = 0, |
| 75 | .imon_offset = 0, |
| 76 | .icc_max = 0, |
| 77 | .voltage_limit = 0 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 78 | }" |
| 79 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 80 | # Enable Root port. |
| 81 | register "PcieRpEnable[3]" = "1" |
| 82 | register "PcieRpEnable[4]" = "1" |
| 83 | register "PcieRpEnable[8]" = "1" |
| 84 | register "PcieRpEnable[16]" = "1" |
| 85 | |
| 86 | # Enable CLKREQ# |
| 87 | register "PcieRpClkReqSupport[3]" = "1" |
| 88 | register "PcieRpClkReqSupport[4]" = "1" |
| 89 | register "PcieRpClkReqSupport[8]" = "1" |
| 90 | register "PcieRpClkReqSupport[16]" = "1" |
| 91 | |
| 92 | # SRCCLKREQ# |
| 93 | register "PcieRpClkReqNumber[3]" = "2" |
| 94 | register "PcieRpClkReqNumber[4]" = "1" |
| 95 | register "PcieRpClkReqNumber[8]" = "6" |
| 96 | register "PcieRpClkReqNumber[16]" = "7" |
| 97 | |
| 98 | register "usb2_ports[0]" = "USB2_PORT_MAX(OC2)" # Type-C Port |
| 99 | register "usb2_ports[1]" = "USB2_PORT_MAX(OC5)" # Front panel |
| 100 | register "usb2_ports[2]" = "USB2_PORT_MAX(OC4)" # Back panel |
| 101 | register "usb2_ports[3]" = "USB2_PORT_MAX(OC4)" # Back panel |
| 102 | register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Back panel-1 |
| 103 | register "usb2_ports[5]" = "USB2_PORT_MAX(OC1)" # Back panel |
| 104 | register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel |
| 105 | register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # Front panel |
| 106 | register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # M.2 BT |
| 107 | register "usb2_ports[9]" = "USB2_PORT_MAX(OC2)" # Front panel |
| 108 | register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel |
| 109 | register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel-1 |
| 110 | register "usb2_ports[12]" = "USB2_PORT_MAX(OC3)" # Back panel |
| 111 | register "usb2_ports[13]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel |
| 112 | |
| 113 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port |
| 114 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Back panel |
| 115 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Back panel |
| 116 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # Back panel-2 |
| 117 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel |
| 118 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Front Panel |
| 119 | register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel |
| 120 | register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel |
| 121 | register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC3)" # Back panel |
| 122 | register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LAN |
| 123 | |
| 124 | register "SsicPortEnable" = "1" # Enable SSIC for WWAN |
| 125 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 126 | register "SataSalpSupport" = "1" |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 127 | register "SataPortsEnable" = "{ |
| 128 | [0] = 1, |
| 129 | [1] = 1, |
| 130 | [2] = 1, |
| 131 | [3] = 1, |
| 132 | [4] = 1, |
| 133 | [5] = 1, |
| 134 | [6] = 1, |
| 135 | [7] = 1, |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 136 | }" |
| 137 | |
| 138 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 139 | register "SerialIoDevMode" = "{ |
| 140 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 141 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 142 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 143 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 144 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 145 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 146 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 147 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 148 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 149 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 150 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 151 | }" |
| 152 | |
| 153 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 154 | register "power_limits_config" = "{ |
| 155 | .tdp_pl2_override = 25, |
| 156 | }" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 157 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 158 | device domain 0 on |
Angel Pons | a6aaef7 | 2021-08-29 11:10:13 +0200 | [diff] [blame] | 159 | device pci 15.2 off end # I2C #2 |
| 160 | device pci 15.3 off end # I2C #3 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 161 | device pci 17.0 on end # SATA |
Angel Pons | 9e97021 | 2021-08-29 09:55:43 +0200 | [diff] [blame] | 162 | device pci 19.2 off end # I2C #4 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 163 | device pci 1c.0 off end # PCI Express Port 1 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 164 | device pci 1c.2 on end # PCI Express Port 3 |
| 165 | device pci 1c.3 on end # PCI Express Port 4 |
| 166 | device pci 1c.4 on end # PCI Express Port 5 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 167 | device pci 1e.4 off end # eMMC |
Felix Singer | 5291952 | 2020-07-29 21:44:36 +0200 | [diff] [blame] | 168 | device pci 1e.6 off end # SDXC |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 169 | device pci 1f.0 on |
| 170 | #chip drivers/pc80/tpm |
| 171 | # device pnp 0c31.0 on end |
| 172 | #end |
| 173 | end # LPC Interface |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 174 | device pci 1f.6 on end # GbE |
| 175 | end |
| 176 | end |