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review.coreboot.org / coreboot / 44e89af6e609874f2f18d30f1e66dce8b5a98eff / . / src / mainboard / intel / kblrvp / variants / rvp8 / overridetree.cb
blob: 8dbaf685a8264a1b0c8a8981b835ad3d487c7e22 [file] [log] [blame]
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]1chip soc/intel/skylake
2
3 # Enable deep Sx states
4 register "deep_s3_enable_ac" = "0"
5 register "deep_s3_enable_dc" = "0"
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]6
7 # FSP Configuration
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]8 register "ScsEmmcEnabled" = "0"
9 register "ScsEmmcHs400Enabled" = "0"
10 register "ScsSdCardEnabled" = "0"
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]11 register "HeciEnabled" = "0"
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]12 register "PmTimerDisabled" = "0"
Nico Huber44e89af2019-02-23 19:24:51 +0100[diff] [blame^]13
14 register "serirq_mode" = "SERIRQ_CONTINUOUS"
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]15
16 # VR Settings Configuration for 5 Domains
17 #+----------------+-------+-------+-------------+-------------+-------+
18 #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
19 #+----------------+-------+-------+-------------+-------------+-------+
20 #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
21 #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
22 #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
23 #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
24 #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
25 #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
26 #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
27 #| IccMax | 7A | 34A | 34A | 35A | 35A |
28 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
29 #+----------------+-------+-------+-------------+-------------+-------+
30 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
31 .vr_config_enable = 1, \
32 .psi1threshold = 0x50, \
33 .psi2threshold = 0x10, \
34 .psi3threshold = 0x4, \
35 .psi3enable = 1, \
36 .psi4enable = 1, \
37 .imon_slope = 0x0, \
38 .imon_offset = 0x0, \
39 .icc_max = 0x0, \
40 .voltage_limit = 0x0 \
41 }"
42
43 register "domain_vr_config[VR_IA_CORE]" = "{
44 .vr_config_enable = 1, \
45 .psi1threshold = 0x50, \
46 .psi2threshold = 0x14, \
47 .psi3threshold = 0x4, \
48 .psi3enable = 1, \
49 .psi4enable = 1, \
50 .imon_slope = 0x0, \
51 .imon_offset = 0x0, \
52 .icc_max = 0x0, \
53 .voltage_limit = 0x0 \
54 }"
55
56 register "domain_vr_config[VR_GT_UNSLICED]" = "{
57 .vr_config_enable = 1, \
58 .psi1threshold = 0x50, \
59 .psi2threshold = 0x14, \
60 .psi3threshold = 0x4, \
61 .psi3enable = 1, \
62 .psi4enable = 1, \
63 .imon_slope = 0x0, \
64 .imon_offset = 0x0, \
65 .icc_max = 0x0 ,\
66 .voltage_limit = 0x0 \
67 }"
68
69 register "domain_vr_config[VR_GT_SLICED]" = "{
70 .vr_config_enable = 1, \
71 .psi1threshold = 0x50, \
72 .psi2threshold = 0x14, \
73 .psi3threshold = 0x4, \
74 .psi3enable = 1, \
75 .psi4enable = 1, \
76 .imon_slope = 0x0, \
77 .imon_offset = 0x0, \
78 .icc_max = 0x0, \
79 .voltage_limit = 0x0 \
80 }"
81
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]82 # Enable Root port.
83 register "PcieRpEnable[3]" = "1"
84 register "PcieRpEnable[4]" = "1"
85 register "PcieRpEnable[8]" = "1"
86 register "PcieRpEnable[16]" = "1"
87
88 # Enable CLKREQ#
89 register "PcieRpClkReqSupport[3]" = "1"
90 register "PcieRpClkReqSupport[4]" = "1"
91 register "PcieRpClkReqSupport[8]" = "1"
92 register "PcieRpClkReqSupport[16]" = "1"
93
94 # SRCCLKREQ#
95 register "PcieRpClkReqNumber[3]" = "2"
96 register "PcieRpClkReqNumber[4]" = "1"
97 register "PcieRpClkReqNumber[8]" = "6"
98 register "PcieRpClkReqNumber[16]" = "7"
99
100 register "usb2_ports[0]" = "USB2_PORT_MAX(OC2)" # Type-C Port
101 register "usb2_ports[1]" = "USB2_PORT_MAX(OC5)" # Front panel
102 register "usb2_ports[2]" = "USB2_PORT_MAX(OC4)" # Back panel
103 register "usb2_ports[3]" = "USB2_PORT_MAX(OC4)" # Back panel
104 register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Back panel-1
105 register "usb2_ports[5]" = "USB2_PORT_MAX(OC1)" # Back panel
106 register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
107 register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # Front panel
108 register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # M.2 BT
109 register "usb2_ports[9]" = "USB2_PORT_MAX(OC2)" # Front panel
110 register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
111 register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel-1
112 register "usb2_ports[12]" = "USB2_PORT_MAX(OC3)" # Back panel
113 register "usb2_ports[13]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
114
115 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
116 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Back panel
117 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Back panel
118 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # Back panel-2
119 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
120 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Front Panel
121 register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel
122 register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel
123 register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC3)" # Back panel
124 register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LAN
125
126 register "SsicPortEnable" = "1" # Enable SSIC for WWAN
127
128 register "EnableSata" = "1"
129 register "SataSalpSupport" = "1"
130 register "SataPortsEnable" = "{ \
131 [0] = 1, \
132 [1] = 1, \
133 [2] = 1, \
134 [3] = 1, \
135 [4] = 1, \
136 [5] = 1, \
137 [6] = 1, \
138 [7] = 1, \
139 }"
140
141 # Must leave UART0 enabled or SD/eMMC will not work as PCI
142 register "SerialIoDevMode" = "{ \
143 [PchSerialIoIndexI2C0] = PchSerialIoPci, \
144 [PchSerialIoIndexI2C1] = PchSerialIoPci, \
145 [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
146 [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
147 [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
148 [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
149 [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
150 [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
151 [PchSerialIoIndexUart0] = PchSerialIoPci, \
152 [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
153 [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
154 }"
155
156 # PL2 override 25W
157 register "tdp_pl2_override" = "25"
158
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]159 # Use default SD card detect GPIO configuration
160 #register "sdcard_cd_gpio_default" = "GPP_D10"
161
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]162 device domain 0 on
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]163 device pci 17.0 on end # SATA
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]164 device pci 19.1 on end # I2C #5
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]165 device pci 1c.0 off end # PCI Express Port 1
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]166 device pci 1c.2 on end # PCI Express Port 3
167 device pci 1c.3 on end # PCI Express Port 4
168 device pci 1c.4 on end # PCI Express Port 5
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]169 device pci 1e.1 on end # UART #1
170 device pci 1e.2 on end # GSPI #0
171 device pci 1e.3 on end # GSPI #1
172 device pci 1e.4 off end # eMMC
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]173 device pci 1f.0 on
174 #chip drivers/pc80/tpm
175 # device pnp 0c31.0 on end
176 #end
177 end # LPC Interface
V Sowmya6b78b732018-01-22 20:23:16 +0530[diff] [blame]178 device pci 1f.6 on end # GbE
179 end
180end