V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 6 | |
| 7 | # FSP Configuration |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 8 | register "ScsEmmcEnabled" = "0" |
| 9 | register "ScsEmmcHs400Enabled" = "0" |
| 10 | register "ScsSdCardEnabled" = "0" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 11 | register "HeciEnabled" = "0" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 12 | register "PmTimerDisabled" = "0" |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 13 | |
| 14 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 15 | |
| 16 | # VR Settings Configuration for 5 Domains |
| 17 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 18 | #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | |
| 19 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 20 | #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | |
| 21 | #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | |
| 22 | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | |
| 23 | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | |
| 24 | #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | |
| 25 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | |
| 26 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 27 | #| IccMax | Auto | Auto | Auto | Auto | Auto | |
| 28 | #| VrVoltageLimit*| 0 | 0 | 0 | 0 | 0 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 29 | #+----------------+-------+-------+-------------+-------------+-------+ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 30 | #* VrVoltageLimit command not sent. |
| 31 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 32 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 33 | .vr_config_enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 34 | .psi1threshold = VR_CFG_AMP(20), \ |
| 35 | .psi2threshold = VR_CFG_AMP(4), \ |
| 36 | .psi3threshold = VR_CFG_AMP(1), \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 37 | .psi3enable = 1, \ |
| 38 | .psi4enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 39 | .imon_slope = 0, \ |
| 40 | .imon_offset = 0, \ |
| 41 | .icc_max = 0, \ |
| 42 | .voltage_limit = 0 \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 43 | }" |
| 44 | |
| 45 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 46 | .vr_config_enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 47 | .psi1threshold = VR_CFG_AMP(20), \ |
| 48 | .psi2threshold = VR_CFG_AMP(5), \ |
| 49 | .psi3threshold = VR_CFG_AMP(1), \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 50 | .psi3enable = 1, \ |
| 51 | .psi4enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 52 | .imon_slope = 0, \ |
| 53 | .imon_offset = 0, \ |
| 54 | .icc_max = 0, \ |
| 55 | .voltage_limit = 0 \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 56 | }" |
| 57 | |
| 58 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 59 | .vr_config_enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 60 | .psi1threshold = VR_CFG_AMP(20), \ |
| 61 | .psi2threshold = VR_CFG_AMP(5), \ |
| 62 | .psi3threshold = VR_CFG_AMP(1), \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 63 | .psi3enable = 1, \ |
| 64 | .psi4enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 65 | .imon_slope = 0, \ |
| 66 | .imon_offset = 0, \ |
| 67 | .icc_max = 0 ,\ |
| 68 | .voltage_limit = 0 \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 69 | }" |
| 70 | |
| 71 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 72 | .vr_config_enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 73 | .psi1threshold = VR_CFG_AMP(20), \ |
| 74 | .psi2threshold = VR_CFG_AMP(5), \ |
| 75 | .psi3threshold = VR_CFG_AMP(1), \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 76 | .psi3enable = 1, \ |
| 77 | .psi4enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 78 | .imon_slope = 0, \ |
| 79 | .imon_offset = 0, \ |
| 80 | .icc_max = 0, \ |
| 81 | .voltage_limit = 0 \ |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 82 | }" |
| 83 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 84 | # Enable Root port. |
| 85 | register "PcieRpEnable[3]" = "1" |
| 86 | register "PcieRpEnable[4]" = "1" |
| 87 | register "PcieRpEnable[8]" = "1" |
| 88 | register "PcieRpEnable[16]" = "1" |
| 89 | |
| 90 | # Enable CLKREQ# |
| 91 | register "PcieRpClkReqSupport[3]" = "1" |
| 92 | register "PcieRpClkReqSupport[4]" = "1" |
| 93 | register "PcieRpClkReqSupport[8]" = "1" |
| 94 | register "PcieRpClkReqSupport[16]" = "1" |
| 95 | |
| 96 | # SRCCLKREQ# |
| 97 | register "PcieRpClkReqNumber[3]" = "2" |
| 98 | register "PcieRpClkReqNumber[4]" = "1" |
| 99 | register "PcieRpClkReqNumber[8]" = "6" |
| 100 | register "PcieRpClkReqNumber[16]" = "7" |
| 101 | |
| 102 | register "usb2_ports[0]" = "USB2_PORT_MAX(OC2)" # Type-C Port |
| 103 | register "usb2_ports[1]" = "USB2_PORT_MAX(OC5)" # Front panel |
| 104 | register "usb2_ports[2]" = "USB2_PORT_MAX(OC4)" # Back panel |
| 105 | register "usb2_ports[3]" = "USB2_PORT_MAX(OC4)" # Back panel |
| 106 | register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Back panel-1 |
| 107 | register "usb2_ports[5]" = "USB2_PORT_MAX(OC1)" # Back panel |
| 108 | register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel |
| 109 | register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # Front panel |
| 110 | register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # M.2 BT |
| 111 | register "usb2_ports[9]" = "USB2_PORT_MAX(OC2)" # Front panel |
| 112 | register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel |
| 113 | register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel-1 |
| 114 | register "usb2_ports[12]" = "USB2_PORT_MAX(OC3)" # Back panel |
| 115 | register "usb2_ports[13]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel |
| 116 | |
| 117 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port |
| 118 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Back panel |
| 119 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Back panel |
| 120 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # Back panel-2 |
| 121 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel |
| 122 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Front Panel |
| 123 | register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel |
| 124 | register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel |
| 125 | register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC3)" # Back panel |
| 126 | register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LAN |
| 127 | |
| 128 | register "SsicPortEnable" = "1" # Enable SSIC for WWAN |
| 129 | |
| 130 | register "EnableSata" = "1" |
| 131 | register "SataSalpSupport" = "1" |
| 132 | register "SataPortsEnable" = "{ \ |
| 133 | [0] = 1, \ |
| 134 | [1] = 1, \ |
| 135 | [2] = 1, \ |
| 136 | [3] = 1, \ |
| 137 | [4] = 1, \ |
| 138 | [5] = 1, \ |
| 139 | [6] = 1, \ |
| 140 | [7] = 1, \ |
| 141 | }" |
| 142 | |
| 143 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 144 | register "SerialIoDevMode" = "{ \ |
| 145 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 146 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 147 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 148 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 149 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ |
| 150 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 151 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 152 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 153 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 154 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 155 | [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ |
| 156 | }" |
| 157 | |
| 158 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame^] | 159 | register "power_limits_config" = "{ |
| 160 | .tdp_pl2_override = 25, |
| 161 | }" |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 162 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 163 | # Use default SD card detect GPIO configuration |
| 164 | #register "sdcard_cd_gpio_default" = "GPP_D10" |
| 165 | |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 166 | device domain 0 on |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 167 | device pci 17.0 on end # SATA |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 168 | device pci 19.1 on end # I2C #5 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 169 | device pci 1c.0 off end # PCI Express Port 1 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 170 | device pci 1c.2 on end # PCI Express Port 3 |
| 171 | device pci 1c.3 on end # PCI Express Port 4 |
| 172 | device pci 1c.4 on end # PCI Express Port 5 |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 173 | device pci 1e.1 on end # UART #1 |
| 174 | device pci 1e.2 on end # GSPI #0 |
| 175 | device pci 1e.3 on end # GSPI #1 |
| 176 | device pci 1e.4 off end # eMMC |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 177 | device pci 1f.0 on |
| 178 | #chip drivers/pc80/tpm |
| 179 | # device pnp 0c31.0 on end |
| 180 | #end |
| 181 | end # LPC Interface |
V Sowmya | 6b78b73 | 2018-01-22 20:23:16 +0530 | [diff] [blame] | 182 | device pci 1f.6 on end # GbE |
| 183 | end |
| 184 | end |