skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 2291c63..8e70c1e 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -95,35 +95,6 @@
register "PcieRpClkReqNumber[8]" = "6"
register "PcieRpClkReqNumber[16]" = "7"
- register "usb2_ports" = "{
- [0] = USB2_PORT_MAX(OC2), /* Type-C Port */
- [1] = USB2_PORT_MAX(OC5), /* Front panel */
- [2] = USB2_PORT_MAX(OC4), /* Back panel */
- [3] = USB2_PORT_MAX(OC4), /* Back panel */
- [4] = USB2_PORT_MAX(OC1), /* Back panel-1 */
- [5] = USB2_PORT_MAX(OC1), /* Back panel */
- [6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
- [7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */
- [8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */
- [9] = USB2_PORT_MAX(OC2), /* Front panel */
- [10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
- [11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */
- [12] = USB2_PORT_MAX(OC3), /* Back panel */
- [13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
- }"
-
- register "usb3_ports" = "{
- [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */
- [1] = USB3_PORT_DEFAULT(OC1), /* Back panel */
- [2] = USB3_PORT_DEFAULT(OC1), /* Back panel */
- [3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */
- [4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
- [5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */
- [6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
- [7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
- [8] = USB3_PORT_DEFAULT(OC3), /* Back panel */
- [9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */
- }"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
@@ -160,6 +131,37 @@
}"
device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MAX(OC2), /* Type-C Port */
+ [1] = USB2_PORT_MAX(OC5), /* Front panel */
+ [2] = USB2_PORT_MAX(OC4), /* Back panel */
+ [3] = USB2_PORT_MAX(OC4), /* Back panel */
+ [4] = USB2_PORT_MAX(OC1), /* Back panel-1 */
+ [5] = USB2_PORT_MAX(OC1), /* Back panel */
+ [6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
+ [7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */
+ [8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */
+ [9] = USB2_PORT_MAX(OC2), /* Front panel */
+ [10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
+ [11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */
+ [12] = USB2_PORT_MAX(OC3), /* Back panel */
+ [13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */
+ [1] = USB3_PORT_DEFAULT(OC1), /* Back panel */
+ [2] = USB3_PORT_DEFAULT(OC1), /* Back panel */
+ [3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */
+ [4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
+ [5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */
+ [6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
+ [7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
+ [8] = USB3_PORT_DEFAULT(OC3), /* Back panel */
+ [9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */
+ }"
+ end
device ref i2c2 off end
device ref i2c3 off end
device ref sata on end