Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 5 | * |
Uwe Hermann | 2bb4acf | 2010-03-01 17:19:55 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 16 | /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ |
Stefan Reinauer | 5e32823 | 2010-03-29 19:19:16 +0000 | [diff] [blame] | 17 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
Kyösti Mälkki | bdaec07 | 2019-03-02 23:18:29 +0200 | [diff] [blame] | 19 | #include <arch/io.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 20 | #include <cf9_reset.h> |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <cpu/intel/romstage.h> |
| 23 | #include <cpu/x86/bist.h> |
| 24 | #include <cpu/x86/lapic.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 25 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 26 | #include <device/pci_ops.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 27 | #include <device/pnp_ops.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 28 | #include <device/pnp_def.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 29 | #include <pc80/mc146818rtc.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <northbridge/intel/i945/i945.h> |
| 31 | #include <northbridge/intel/i945/raminit.h> |
| 32 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 33 | #include <southbridge/intel/common/pmclib.h> |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 34 | #include <superio/winbond/common/winbond.h> |
| 35 | #include <superio/winbond/w83627thg/w83627thg.h> |
| 36 | |
| 37 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 38 | |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 39 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 40 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 41 | static void ich7_enable_lpc(void) |
| 42 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 43 | int lpt_en = 0; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 44 | if (read_option(lpt, 0) != 0) |
| 45 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 46 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 47 | /* Enable Serial IRQ */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 48 | pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 49 | /* Set COM1/COM2 decode range */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 50 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 51 | /* Enable COM1/COM2/KBD/SuperIO1+2 */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 52 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN |
| 53 | | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN |
| 54 | | COMB_LPC_EN | lpt_en); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 55 | /* Enable HWM at 0xa00 */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 56 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 57 | /* COM3 decode */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 58 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 59 | /* COM4 decode */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 60 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 61 | /* io 0x300 decode */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 62 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 63 | } |
| 64 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 65 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 66 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 67 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 68 | * but safe anyways" method. |
| 69 | */ |
| 70 | static void early_superio_config_w83627thg(void) |
| 71 | { |
Antonello Dettori | 9ec1123 | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 72 | pnp_devfn_t dev; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 73 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 74 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 75 | pnp_enter_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 76 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 77 | pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 78 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 79 | pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ |
| 80 | pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 81 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 82 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 83 | pnp_set_logical_device(dev); |
| 84 | pnp_set_enable(dev, 0); |
| 85 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 86 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 87 | pnp_set_enable(dev, 1); |
| 88 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 89 | dev = PNP_DEV(0x2e, W83627THG_SP2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 90 | pnp_set_logical_device(dev); |
| 91 | pnp_set_enable(dev, 0); |
| 92 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 93 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 94 | pnp_set_enable(dev, 1); |
| 95 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 96 | dev = PNP_DEV(0x2e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 97 | pnp_set_logical_device(dev); |
| 98 | pnp_set_enable(dev, 0); |
| 99 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 100 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 101 | pnp_set_enable(dev, 1); |
| 102 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 103 | dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 104 | pnp_set_logical_device(dev); |
| 105 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 106 | pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 107 | pnp_set_enable(dev, 1); |
| 108 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 109 | dev = PNP_DEV(0x2e, W83627THG_GPIO2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 110 | pnp_set_logical_device(dev); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 111 | pnp_set_enable(dev, 1); /* Just enable it */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 112 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 113 | dev = PNP_DEV(0x2e, W83627THG_GPIO3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 114 | pnp_set_logical_device(dev); |
| 115 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 116 | pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ |
| 117 | pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ |
| 118 | pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 119 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 120 | dev = PNP_DEV(0x2e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 121 | pnp_set_logical_device(dev); |
| 122 | pnp_set_enable(dev, 0); |
| 123 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 124 | dev = PNP_DEV(0x2e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 125 | pnp_set_logical_device(dev); |
| 126 | pnp_set_enable(dev, 0); |
| 127 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 128 | /* Enable HWM */ |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 129 | dev = PNP_DEV(0x2e, W83627THG_HWM); |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 130 | pnp_set_logical_device(dev); |
| 131 | pnp_set_enable(dev, 0); |
| 132 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 133 | pnp_set_enable(dev, 1); |
| 134 | |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 135 | pnp_exit_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 136 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 137 | dev = PNP_DEV(0x4e, W83627THG_SP1); |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 138 | pnp_enter_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 139 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 140 | pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 141 | pnp_set_enable(dev, 0); |
| 142 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); |
| 143 | pnp_set_irq(dev, PNP_IDX_IRQ0, 11); |
| 144 | pnp_set_enable(dev, 1); |
| 145 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 146 | dev = PNP_DEV(0x4e, W83627THG_SP2); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 147 | pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 148 | pnp_set_enable(dev, 0); |
| 149 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); |
| 150 | pnp_set_irq(dev, PNP_IDX_IRQ0, 10); |
| 151 | pnp_set_enable(dev, 1); |
| 152 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 153 | dev = PNP_DEV(0x4e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 154 | pnp_set_logical_device(dev); |
| 155 | pnp_set_enable(dev, 0); |
| 156 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 157 | dev = PNP_DEV(0x4e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 158 | pnp_set_logical_device(dev); |
| 159 | pnp_set_enable(dev, 0); |
| 160 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 161 | dev = PNP_DEV(0x4e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 162 | pnp_set_logical_device(dev); |
| 163 | pnp_set_enable(dev, 0); |
| 164 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); |
| 165 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); |
| 166 | |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 167 | pnp_exit_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | static void rcba_config(void) |
| 171 | { |
| 172 | /* Set up virtual channel 0 */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 173 | |
| 174 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 175 | RCBA32(D31IP) = 0x00042210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 176 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 177 | RCBA32(D28IP) = 0x00214321; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 178 | |
| 179 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 180 | RCBA16(D31IR) = 0x0132; |
| 181 | RCBA16(D30IR) = 0x3241; |
| 182 | RCBA16(D29IR) = 0x0237; |
| 183 | RCBA16(D28IR) = 0x3210; |
| 184 | RCBA16(D27IR) = 0x3210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 185 | |
| 186 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 187 | RCBA8(OIC) = 0x03; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 188 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 189 | /* Enable PCIe Root Port Clock Gate */ |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 190 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | static void early_ich7_init(void) |
| 194 | { |
| 195 | uint8_t reg8; |
| 196 | uint32_t reg32; |
| 197 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 198 | /* program secondary mlt XXX byte? */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 199 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 200 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 201 | /* reset rtc power status */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 202 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 203 | reg8 &= ~(1 << 2); |
| 204 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 205 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 206 | /* usb transient disconnect */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 207 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 208 | reg8 |= (3 << 0); |
| 209 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 210 | |
| 211 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 212 | reg32 |= (1 << 29) | (1 << 17); |
| 213 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 214 | |
| 215 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 216 | reg32 |= (1 << 31) | (1 << 27); |
| 217 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 218 | |
| 219 | RCBA32(0x0088) = 0x0011d000; |
| 220 | RCBA16(0x01fc) = 0x060f; |
| 221 | RCBA32(0x01f4) = 0x86000040; |
| 222 | RCBA32(0x0214) = 0x10030549; |
| 223 | RCBA32(0x0218) = 0x00020504; |
| 224 | RCBA8(0x0220) = 0xc5; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 225 | reg32 = RCBA32(GCS); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 226 | reg32 |= (1 << 6); |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 227 | RCBA32(GCS) = reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 228 | reg32 = RCBA32(0x3430); |
| 229 | reg32 &= ~(3 << 0); |
| 230 | reg32 |= (1 << 0); |
| 231 | RCBA32(0x3430) = reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 232 | RCBA16(0x0200) = 0x2008; |
| 233 | RCBA8(0x2027) = 0x0d; |
| 234 | RCBA16(0x3e08) |= (1 << 7); |
| 235 | RCBA16(0x3e48) |= (1 << 7); |
| 236 | RCBA32(0x3e0e) |= (1 << 7); |
| 237 | RCBA32(0x3e4e) |= (1 << 7); |
| 238 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 239 | /* next step only on ich7m b0 and later: */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 240 | reg32 = RCBA32(0x2034); |
| 241 | reg32 &= ~(0x0f << 16); |
| 242 | reg32 |= (5 << 16); |
| 243 | RCBA32(0x2034) = reg32; |
| 244 | } |
| 245 | |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 246 | void mainboard_romstage_entry(unsigned long bist) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 247 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 248 | int s3resume = 0; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 249 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 250 | if (bist == 0) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 251 | enable_lapic(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 252 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 253 | /* Force PCIRST# */ |
| 254 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 255 | udelay(200 * 1000); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 256 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 257 | |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 258 | ich7_enable_lpc(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 259 | early_superio_config_w83627thg(); |
| 260 | |
| 261 | /* Set up the console */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 262 | console_init(); |
| 263 | |
| 264 | /* Halt if there was a built in self test failure */ |
| 265 | report_bist_failure(bist); |
| 266 | |
| 267 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 268 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 269 | system_reset(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 270 | } |
| 271 | |
| 272 | /* Perform some early chipset initialization required |
| 273 | * before RAM initialization can work |
| 274 | */ |
| 275 | i945_early_initialization(); |
| 276 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 277 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 278 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 279 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 280 | enable_smbus(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 281 | |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 282 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 283 | dump_spd_registers(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 284 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 285 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 286 | |
| 287 | /* Perform some initialization that must run before stage2 */ |
| 288 | early_ich7_init(); |
| 289 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 290 | /* This should probably go away. Until now it is required |
| 291 | * and mainboard specific |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 292 | */ |
| 293 | rcba_config(); |
| 294 | |
| 295 | /* Chipset Errata! */ |
| 296 | fixup_i945_errata(); |
| 297 | |
| 298 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 299 | i945_late_initialization(s3resume); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 300 | } |