Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 4 | #include <cbfs.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <fsp/api.h> |
| 9 | #include <fsp/ppi/mp_service_ppi.h> |
| 10 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 11 | #include <option.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 12 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 13 | #include <intelblocks/lpss.h> |
| 14 | #include <intelblocks/xdci.h> |
| 15 | #include <intelpch/lockdown.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 16 | #include <intelblocks/tcss.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <soc/gpio_soc_defs.h> |
| 18 | #include <soc/intel/common/vbt.h> |
| 19 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 20 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 21 | #include <soc/ramstage.h> |
| 22 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 23 | #include <stdlib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 25 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 26 | |
| 27 | /* THC assignment definition */ |
| 28 | #define THC_NONE 0 |
| 29 | #define THC_0 1 |
| 30 | #define THC_1 2 |
| 31 | |
| 32 | /* SATA DEVSLP idle timeout default values */ |
| 33 | #define DEF_DMVAL 15 |
| 34 | #define DEF_DITOVAL 625 |
| 35 | |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 36 | /* |
| 37 | * ME End of Post configuration |
| 38 | * 0 - Disable EOP. |
| 39 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 40 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 41 | */ |
| 42 | enum fsp_end_of_post { |
| 43 | EOP_DISABLE = 0, |
| 44 | EOP_PEI = 1, |
| 45 | EOP_DXE = 2, |
| 46 | }; |
| 47 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 48 | static const struct slot_irq_constraints irq_constraints[] = { |
| 49 | { |
| 50 | .slot = SA_DEV_SLOT_IGD, |
| 51 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 52 | /* INTERRUPT_PIN is RO/0x01 */ |
| 53 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 54 | }, |
| 55 | }, |
| 56 | { |
| 57 | .slot = SA_DEV_SLOT_DPTF, |
| 58 | .fns = { |
| 59 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 60 | }, |
| 61 | }, |
| 62 | { |
| 63 | .slot = SA_DEV_SLOT_IPU, |
| 64 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 65 | /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, |
| 66 | but S0ix fails when not set to 16 (b/193434192) */ |
| 67 | FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 68 | }, |
| 69 | }, |
| 70 | { |
| 71 | .slot = SA_DEV_SLOT_CPU_6, |
| 72 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 73 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), |
| 74 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 75 | }, |
| 76 | }, |
| 77 | { |
| 78 | .slot = SA_DEV_SLOT_TBT, |
| 79 | .fns = { |
| 80 | ANY_PIRQ(SA_DEVFN_TBT0), |
| 81 | ANY_PIRQ(SA_DEVFN_TBT1), |
| 82 | ANY_PIRQ(SA_DEVFN_TBT2), |
| 83 | ANY_PIRQ(SA_DEVFN_TBT3), |
| 84 | }, |
| 85 | }, |
| 86 | { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 87 | .slot = SA_DEV_SLOT_GNA, |
| 88 | .fns = { |
| 89 | /* INTERRUPT_PIN is RO/0x01 */ |
| 90 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 91 | }, |
| 92 | }, |
| 93 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 94 | .slot = SA_DEV_SLOT_TCSS, |
| 95 | .fns = { |
| 96 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 97 | ANY_PIRQ(SA_DEVFN_TCSS_XDCI), |
| 98 | }, |
| 99 | }, |
| 100 | { |
| 101 | .slot = PCH_DEV_SLOT_SIO0, |
| 102 | .fns = { |
| 103 | DIRECT_IRQ(PCH_DEVFN_I2C6), |
| 104 | DIRECT_IRQ(PCH_DEVFN_I2C7), |
| 105 | ANY_PIRQ(PCH_DEVFN_THC0), |
| 106 | ANY_PIRQ(PCH_DEVFN_THC1), |
| 107 | }, |
| 108 | }, |
| 109 | { |
| 110 | .slot = PCH_DEV_SLOT_SIO6, |
| 111 | .fns = { |
| 112 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 113 | DIRECT_IRQ(PCH_DEVFN_UART4), |
| 114 | DIRECT_IRQ(PCH_DEVFN_UART5), |
| 115 | DIRECT_IRQ(PCH_DEVFN_UART6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 116 | }, |
| 117 | }, |
| 118 | { |
| 119 | .slot = PCH_DEV_SLOT_ISH, |
| 120 | .fns = { |
| 121 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 122 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 123 | ANY_PIRQ(PCH_DEVFN_UFS), |
| 124 | }, |
| 125 | }, |
| 126 | { |
| 127 | .slot = PCH_DEV_SLOT_SIO2, |
| 128 | .fns = { |
| 129 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 130 | DIRECT_IRQ(PCH_DEVFN_GSPI4), |
| 131 | DIRECT_IRQ(PCH_DEVFN_GSPI5), |
| 132 | DIRECT_IRQ(PCH_DEVFN_GSPI6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 133 | }, |
| 134 | }, |
| 135 | { |
| 136 | .slot = PCH_DEV_SLOT_XHCI, |
| 137 | .fns = { |
| 138 | ANY_PIRQ(PCH_DEVFN_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 139 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 140 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 141 | }, |
| 142 | }, |
| 143 | { |
| 144 | .slot = PCH_DEV_SLOT_SIO3, |
| 145 | .fns = { |
| 146 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 147 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 148 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 149 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 150 | }, |
| 151 | }, |
| 152 | { |
| 153 | .slot = PCH_DEV_SLOT_CSE, |
| 154 | .fns = { |
| 155 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 156 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 157 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 158 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 159 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 160 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 161 | }, |
| 162 | }, |
| 163 | { |
| 164 | .slot = PCH_DEV_SLOT_SATA, |
| 165 | .fns = { |
| 166 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 167 | }, |
| 168 | }, |
| 169 | { |
| 170 | .slot = PCH_DEV_SLOT_SIO4, |
| 171 | .fns = { |
| 172 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 173 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 174 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 175 | }, |
| 176 | }, |
| 177 | { |
| 178 | .slot = PCH_DEV_SLOT_PCIE, |
| 179 | .fns = { |
| 180 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 181 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 182 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 183 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 184 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 185 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 186 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 187 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 188 | }, |
| 189 | }, |
| 190 | { |
| 191 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 192 | .fns = { |
| 193 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 194 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 195 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 196 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 197 | }, |
| 198 | }, |
| 199 | { |
| 200 | .slot = PCH_DEV_SLOT_SIO5, |
| 201 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 202 | /* UART0 shares an interrupt line with TSN0, so must use |
| 203 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 204 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 205 | /* UART1 shares an interrupt line with TSN1, so must use |
| 206 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 207 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 208 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 209 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 210 | }, |
| 211 | }, |
| 212 | { |
| 213 | .slot = PCH_DEV_SLOT_ESPI, |
| 214 | .fns = { |
| 215 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 216 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 217 | ANY_PIRQ(PCH_DEVFN_GBE), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 218 | /* INTERRUPT_PIN is RO/0x01 */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 219 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 220 | }, |
| 221 | }, |
| 222 | }; |
| 223 | |
| 224 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 225 | { |
| 226 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 227 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 228 | size_t pch_total = 0; |
| 229 | size_t cfg_count = 0; |
| 230 | |
| 231 | if (!entry) |
| 232 | return NULL; |
| 233 | |
| 234 | /* Count PCH devices */ |
| 235 | while (entry) { |
| 236 | if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) |
| 237 | ++pch_total; |
| 238 | entry = entry->next; |
| 239 | } |
| 240 | |
| 241 | /* Convert PCH device entries to FSP format */ |
| 242 | config = calloc(pch_total, sizeof(*config)); |
| 243 | entry = get_cached_pci_irqs(); |
| 244 | while (entry) { |
| 245 | if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { |
| 246 | entry = entry->next; |
| 247 | continue; |
| 248 | } |
| 249 | |
| 250 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 251 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 252 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 253 | config[cfg_count].Irq = entry->irq; |
| 254 | ++cfg_count; |
| 255 | |
| 256 | entry = entry->next; |
| 257 | } |
| 258 | |
| 259 | *out_count = cfg_count; |
| 260 | |
| 261 | return config; |
| 262 | } |
| 263 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 264 | /* |
| 265 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 266 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 267 | * In order to ensure that mainboard setting does not disable L1 substates |
| 268 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 269 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 270 | * value is set in fsp_params. |
| 271 | * 0: Use FSP UPD default |
| 272 | * 1: Disable L1 substates |
| 273 | * 2: Use L1.1 |
| 274 | * 3: Use L1.2 (FSP UPD default) |
| 275 | */ |
| 276 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 277 | { |
| 278 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 279 | ctl = L1_SS_L1_2; |
| 280 | return ctl - 1; |
| 281 | } |
| 282 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 283 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 284 | { |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 285 | /* Override settings per board. */ |
| 286 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 287 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 288 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 289 | const struct soc_intel_alderlake_config *config) |
| 290 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 291 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 292 | s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 293 | |
| 294 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 295 | s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 296 | s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 297 | s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 301 | s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 302 | } |
| 303 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 304 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 305 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 306 | { |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 307 | const struct microcode *microcode_file; |
| 308 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 309 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 310 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 311 | microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); |
| 312 | |
| 313 | if ((microcode_file != NULL) && (microcode_len != 0)) { |
| 314 | /* Update CPU Microcode patch base address/size */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 315 | s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file; |
| 316 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 317 | } |
| 318 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 319 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 320 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 321 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 322 | } |
| 323 | |
| 324 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 325 | const struct soc_intel_alderlake_config *config) |
| 326 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 327 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 328 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 329 | |
| 330 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 331 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
| 332 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 333 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 334 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 335 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 336 | const struct soc_intel_alderlake_config *config) |
| 337 | { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 338 | s_cfg->TcssAuxOri = config->TcssAuxOri; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 339 | |
| 340 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 341 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 342 | |
| 343 | /* |
| 344 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 345 | * evaluate this UPD value and skip sending command. There will be no |
| 346 | * delay for command completion. |
| 347 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 348 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 349 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 350 | /* D3Hot and D3Cold for TCSS */ |
| 351 | s_cfg->D3HotEnable = !config->TcssD3HotDisable; |
| 352 | s_cfg->D3ColdEnable = !config->TcssD3ColdDisable; |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 353 | |
| 354 | s_cfg->UsbTcPortEn = 0; |
| 355 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
| 356 | /* TCSS xHCI --> Root Hub --> Type-C Port */ |
| 357 | const struct device_path port_path[] = { |
| 358 | {.type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_TCSS_XHCI}, |
| 359 | {.type = DEVICE_PATH_USB, .usb.port_type = 0, .usb.port_id = 0}, |
| 360 | {.type = DEVICE_PATH_USB, .usb.port_type = 3, .usb.port_id = i} }; |
| 361 | const struct device *port = find_dev_nested_path(pci_root_bus(), port_path, |
| 362 | ARRAY_SIZE(port_path)); |
| 363 | |
| 364 | if (is_dev_enabled(port)) |
| 365 | s_cfg->UsbTcPortEn |= BIT(i); |
| 366 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 367 | } |
| 368 | |
| 369 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 370 | const struct soc_intel_alderlake_config *config) |
| 371 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 372 | /* Chipset Lockdown */ |
| 373 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 374 | s_cfg->PchLockDownGlobalSmi = 0; |
| 375 | s_cfg->PchLockDownBiosInterface = 0; |
| 376 | s_cfg->PchUnlockGpioPads = 1; |
| 377 | s_cfg->RtcMemoryLock = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 378 | } else { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 379 | s_cfg->PchLockDownGlobalSmi = 1; |
| 380 | s_cfg->PchLockDownBiosInterface = 1; |
| 381 | s_cfg->PchUnlockGpioPads = 0; |
| 382 | s_cfg->RtcMemoryLock = 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 383 | } |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 384 | |
| 385 | /* coreboot will send EOP before loading payload */ |
| 386 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 387 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 388 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 389 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 390 | const struct soc_intel_alderlake_config *config) |
| 391 | { |
| 392 | int i; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 393 | /* USB */ |
| 394 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 395 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 396 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 397 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 398 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 399 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 400 | |
| 401 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 402 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 403 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 404 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 408 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 409 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 410 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 411 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 412 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 413 | |
| 414 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 415 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 416 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 417 | } |
| 418 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 419 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 420 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 421 | config->usb3_ports[i].tx_downscale_amp; |
| 422 | } |
| 423 | } |
| 424 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 425 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 426 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 427 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 428 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 429 | } |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 430 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 431 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 432 | const struct soc_intel_alderlake_config *config) |
| 433 | { |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 434 | s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 435 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 436 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 437 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 438 | const struct soc_intel_alderlake_config *config) |
| 439 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 440 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 441 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 442 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 443 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 444 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 445 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 446 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 447 | const struct soc_intel_alderlake_config *config) |
| 448 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 449 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 450 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 451 | if (s_cfg->SataEnable) { |
| 452 | s_cfg->SataMode = config->SataMode; |
| 453 | s_cfg->SataSalpSupport = config->SataSalpSupport; |
| 454 | memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable, |
| 455 | sizeof(s_cfg->SataPortsEnable)); |
| 456 | memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp, |
| 457 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | /* |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 461 | * Power Optimizer for SATA. |
| 462 | * SataPwrOptimizeDisable is default to 0. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 463 | * Boards not needing the optimizers explicitly disables them by setting |
| 464 | * these disable variables to 1 in devicetree overrides. |
| 465 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 466 | s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 467 | /* |
| 468 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 469 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 470 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 471 | * The default values can be changed from devicetree. |
| 472 | */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 473 | for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 474 | if (config->SataPortsEnableDitoConfig[i]) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 475 | s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 476 | s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 477 | } |
| 478 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 479 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 480 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 481 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 482 | const struct soc_intel_alderlake_config *config) |
| 483 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 484 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 485 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 486 | |
| 487 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 488 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 489 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 490 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 491 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 492 | const struct soc_intel_alderlake_config *config) |
| 493 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 494 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 495 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 496 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 497 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 498 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 499 | const struct soc_intel_alderlake_config *config) |
| 500 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 501 | /* CNVi */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 502 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
| 503 | s_cfg->CnviBtCore = config->CnviBtCore; |
| 504 | s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 505 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 506 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 507 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 508 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 509 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 510 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 511 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 512 | const struct soc_intel_alderlake_config *config) |
| 513 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 514 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 515 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 516 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 517 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 518 | static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, |
| 519 | const struct soc_intel_alderlake_config *config) |
| 520 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 521 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 522 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 523 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 524 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 525 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 526 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 527 | const struct soc_intel_alderlake_config *config) |
| 528 | { |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 529 | /* USB4/TBT */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 530 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 531 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 532 | } |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 533 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 534 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 535 | const struct soc_intel_alderlake_config *config) |
| 536 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 537 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 538 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 539 | s_cfg->Enable8254ClockGating = !use_8254; |
| 540 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 541 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 542 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 543 | static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, |
| 544 | const struct soc_intel_alderlake_config *config) |
| 545 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 546 | /* Enable Hybrid storage auto detection */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 547 | s_cfg->HybridStorageMode = config->HybridStorageMode; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 548 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 549 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 550 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 551 | const struct soc_intel_alderlake_config *config) |
| 552 | { |
| 553 | uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
| 554 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 555 | if (!(enable_mask & BIT(i))) |
| 556 | continue; |
| 557 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 558 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 559 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 560 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 561 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 562 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 563 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 564 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 565 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 566 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 567 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 568 | const struct soc_intel_alderlake_config *config) |
| 569 | { |
| 570 | /* |
| 571 | * Power Optimizer for DMI |
| 572 | * DmiPwrOptimizeDisable is default to 0. |
| 573 | * Boards not needing the optimizers explicitly disables them by setting |
| 574 | * these disable variables to 1 in devicetree overrides. |
| 575 | */ |
| 576 | s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 577 | s_cfg->PmSupport = 1; |
| 578 | s_cfg->Hwp = 1; |
| 579 | s_cfg->Cx = 1; |
| 580 | s_cfg->PsOnEnable = 1; |
V Sowmya | 844dcb3 | 2021-06-21 10:03:53 +0530 | [diff] [blame] | 581 | /* Enable the energy efficient turbo mode */ |
| 582 | s_cfg->EnergyEfficientTurbo = 1; |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 583 | s_cfg->PkgCStateLimit = LIMIT_AUTO; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 584 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 585 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 586 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 587 | const struct soc_intel_alderlake_config *config) |
| 588 | { |
| 589 | if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) |
| 590 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 591 | |
| 592 | size_t pch_count = 0; |
| 593 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 594 | |
| 595 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 596 | s_cfg->NumOfDevIntConfig = pch_count; |
| 597 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 598 | } |
| 599 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 600 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 601 | const struct soc_intel_alderlake_config *config) |
| 602 | { |
| 603 | /* PCH FIVR settings override */ |
| 604 | if (!config->ext_fivr_settings.configure_ext_fivr) |
| 605 | return; |
| 606 | |
| 607 | s_cfg->PchFivrExtV1p05RailEnabledStates = |
| 608 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 609 | |
| 610 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = |
| 611 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 612 | |
| 613 | s_cfg->PchFivrExtVnnRailEnabledStates = |
| 614 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 615 | |
| 616 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = |
| 617 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 618 | |
| 619 | s_cfg->PchFivrExtVnnRailSxEnabledStates = |
| 620 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 621 | |
| 622 | /* Convert the voltages to increments of 2.5mv */ |
| 623 | s_cfg->PchFivrExtV1p05RailVoltage = |
| 624 | (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25; |
| 625 | |
| 626 | s_cfg->PchFivrExtVnnRailVoltage = |
| 627 | (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25; |
| 628 | |
| 629 | s_cfg->PchFivrExtVnnRailSxVoltage = |
| 630 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25); |
| 631 | |
| 632 | s_cfg->PchFivrExtV1p05RailIccMaximum = |
| 633 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 634 | |
| 635 | s_cfg->PchFivrExtVnnRailIccMaximum = |
| 636 | config->ext_fivr_settings.vnn_icc_max_ma; |
| 637 | } |
| 638 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 639 | static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) |
| 640 | { |
| 641 | /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ |
| 642 | s_arch_cfg->EnableMultiPhaseSiliconInit = 1; |
| 643 | } |
| 644 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 645 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 646 | struct soc_intel_alderlake_config *config) |
| 647 | { |
| 648 | /* Override settings per board if required. */ |
| 649 | mainboard_update_soc_chip_config(config); |
| 650 | |
V Sowmya | 6464c2a | 2021-06-25 10:20:25 +0530 | [diff] [blame] | 651 | const void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 652 | const struct soc_intel_alderlake_config *config) = { |
| 653 | fill_fsps_lpss_params, |
| 654 | fill_fsps_cpu_params, |
| 655 | fill_fsps_igd_params, |
| 656 | fill_fsps_tcss_params, |
| 657 | fill_fsps_chipset_lockdown_params, |
| 658 | fill_fsps_xhci_params, |
| 659 | fill_fsps_xdci_params, |
| 660 | fill_fsps_uart_params, |
| 661 | fill_fsps_sata_params, |
| 662 | fill_fsps_thermal_params, |
| 663 | fill_fsps_lan_params, |
| 664 | fill_fsps_cnvi_params, |
| 665 | fill_fsps_vmd_params, |
| 666 | fill_fsps_thc_params, |
| 667 | fill_fsps_tbt_params, |
| 668 | fill_fsps_8254_params, |
| 669 | fill_fsps_storage_params, |
| 670 | fill_fsps_pcie_params, |
| 671 | fill_fsps_misc_power_params, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 672 | fill_fsps_irq_params, |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 673 | fill_fsps_fivr_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 674 | }; |
| 675 | |
| 676 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 677 | fill_fsps_params[i](s_cfg, config); |
| 678 | } |
| 679 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 680 | /* UPD parameters to be initialized before SiliconInit */ |
| 681 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 682 | { |
| 683 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 684 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 685 | FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; |
| 686 | |
| 687 | config = config_of_soc(); |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 688 | arch_silicon_init_params(s_arch_cfg); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 689 | soc_silicon_init_params(s_cfg, config); |
| 690 | mainboard_silicon_init_params(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 691 | } |
| 692 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 693 | /* |
| 694 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 695 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 696 | * Phase | FSP return point | Purpose |
| 697 | * ------- + ------------------------------------------------ + ------------------------------- |
| 698 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 699 | */ |
| 700 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 701 | { |
| 702 | switch (phase_index) { |
| 703 | case 1: |
| 704 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 705 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 706 | __FILE__, __func__); |
| 707 | |
| 708 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 709 | const config_t *config = config_of_soc(); |
| 710 | tcss_configure(config->typec_aux_bias_pads); |
| 711 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 712 | break; |
| 713 | default: |
| 714 | break; |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 719 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 720 | { |
| 721 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 722 | } |