Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3 | #include <console/console.h> |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 5 | #include <string.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 6 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 9 | #include <device/smbus_host.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 10 | #include <cpu/x86/msr.h> |
Arthur Heymans | e7dd380 | 2019-11-25 12:09:33 +0100 | [diff] [blame] | 11 | #include <cpu/x86/cache.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 12 | #include <cbmem.h> |
Elyes HAOUAS | d45f338 | 2019-04-28 18:04:35 +0200 | [diff] [blame] | 13 | #include <cf9_reset.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 14 | #include <ip_checksum.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 15 | #include <option.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 16 | #include <device/pci_def.h> |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 17 | #include <device/device.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 18 | #include <halt.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 19 | #include <spd.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 20 | #include <timestamp.h> |
| 21 | #include <cpu/x86/mtrr.h> |
| 22 | #include <cpu/intel/speedstep.h> |
| 23 | #include <cpu/intel/turbo.h> |
Arthur Heymans | dc71e25 | 2018-01-29 10:14:48 +0100 | [diff] [blame] | 24 | #include <mrc_cache.h> |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 25 | #include <southbridge/intel/ibexpeak/me.h> |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 26 | #include <southbridge/intel/common/pmbase.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 27 | #include <delay.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 28 | #include <types.h> |
| 29 | |
| 30 | #include "chip.h" |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 31 | #include "ironlake.h" |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 32 | #include "raminit.h" |
Angel Pons | 18a55cd | 2019-08-14 20:46:00 +0200 | [diff] [blame] | 33 | #include "raminit_tables.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 34 | |
| 35 | #define NORTHBRIDGE PCI_DEV(0, 0, 0) |
| 36 | #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) |
| 37 | #define GMA PCI_DEV (0, 0x2, 0x0) |
| 38 | #define HECIDEV PCI_DEV(0, 0x16, 0) |
| 39 | #define HECIBAR 0x10 |
| 40 | |
| 41 | #define FOR_ALL_RANKS \ |
| 42 | for (channel = 0; channel < NUM_CHANNELS; channel++) \ |
| 43 | for (slot = 0; slot < NUM_SLOTS; slot++) \ |
| 44 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 45 | |
| 46 | #define FOR_POPULATED_RANKS \ |
| 47 | for (channel = 0; channel < NUM_CHANNELS; channel++) \ |
| 48 | for (slot = 0; slot < NUM_SLOTS; slot++) \ |
| 49 | for (rank = 0; rank < NUM_RANKS; rank++) \ |
| 50 | if (info->populated_ranks[channel][slot][rank]) |
| 51 | |
| 52 | #define FOR_POPULATED_RANKS_BACKWARDS \ |
| 53 | for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) \ |
| 54 | for (slot = 0; slot < NUM_SLOTS; slot++) \ |
| 55 | for (rank = 0; rank < NUM_RANKS; rank++) \ |
| 56 | if (info->populated_ranks[channel][slot][rank]) |
| 57 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 58 | #include <lib.h> /* Prototypes */ |
| 59 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 60 | typedef struct _u128 { |
| 61 | u64 lo; |
| 62 | u64 hi; |
| 63 | } u128; |
| 64 | |
| 65 | static void read128(u32 addr, u64 * out) |
| 66 | { |
| 67 | u128 ret; |
| 68 | u128 stor; |
| 69 | asm volatile ("movdqu %%xmm0, %0\n" |
| 70 | "movdqa (%2), %%xmm0\n" |
| 71 | "movdqu %%xmm0, %1\n" |
| 72 | "movdqu %0, %%xmm0":"+m" (stor), "=m"(ret):"r"(addr)); |
| 73 | out[0] = ret.lo; |
| 74 | out[1] = ret.hi; |
| 75 | } |
| 76 | |
Angel Pons | c2d6f5f | 2020-12-11 23:48:51 +0100 | [diff] [blame] | 77 | /* |
| 78 | * Ironlake memory I/O timings are located in scan chains, accessible |
| 79 | * through MCHBAR register groups. Each channel has a scan chain, and |
| 80 | * there's a global scan chain too. Each chain is broken into smaller |
| 81 | * sections of N bits, where N <= 32. Each section allows reading and |
| 82 | * writing a certain parameter. Each section contains N - 2 data bits |
| 83 | * and two additional bits: a Mask bit, and a Halt bit. |
| 84 | */ |
| 85 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 86 | /* OK */ |
| 87 | static void write_1d0(u32 val, u16 addr, int bits, int flag) |
| 88 | { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 89 | MCHBAR32(0x1d0) = 0; |
| 90 | while (MCHBAR32(0x1d0) & 0x800000) |
| 91 | ; |
| 92 | MCHBAR32(0x1d4) = |
| 93 | (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits); |
| 94 | MCHBAR32(0x1d0) = 0x40000000 | addr; |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 95 | while (MCHBAR32(0x1d0) & 0x800000) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 96 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | /* OK */ |
| 100 | static u16 read_1d0(u16 addr, int split) |
| 101 | { |
| 102 | u32 val; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 103 | MCHBAR32(0x1d0) = 0; |
| 104 | while (MCHBAR32(0x1d0) & 0x800000) |
| 105 | ; |
| 106 | MCHBAR32(0x1d0) = |
| 107 | 0x80000000 | (((MCHBAR8(0x246) >> 2) & 3) + 0x361 - addr); |
| 108 | while (MCHBAR32(0x1d0) & 0x800000) |
| 109 | ; |
| 110 | val = MCHBAR32(0x1d8); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 111 | write_1d0(0, 0x33d, 0, 0); |
| 112 | write_1d0(0, 0x33d, 0, 0); |
| 113 | val &= ((1 << split) - 1); |
| 114 | // printk (BIOS_ERR, "R1D0C [%x] => %x\n", addr, val); |
| 115 | return val; |
| 116 | } |
| 117 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 118 | static void write32p(uintptr_t addr, uint32_t val) |
| 119 | { |
| 120 | write32((void *)addr, val); |
| 121 | } |
| 122 | |
| 123 | static uint32_t read32p(uintptr_t addr) |
| 124 | { |
| 125 | return read32((void *)addr); |
| 126 | } |
| 127 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 128 | static void sfence(void) |
| 129 | { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 130 | asm volatile ("sfence"); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static inline u16 get_lane_offset(int slot, int rank, int lane) |
| 134 | { |
| 135 | return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - |
| 136 | 0x452 * (lane == 8); |
| 137 | } |
| 138 | |
| 139 | static inline u16 get_timing_register_addr(int lane, int tm, int slot, int rank) |
| 140 | { |
| 141 | const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c }; |
| 142 | return get_lane_offset(slot, rank, lane) + offs[(tm + 3) % 4]; |
| 143 | } |
| 144 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 145 | static u32 gav_real(int line, u32 in) |
| 146 | { |
| 147 | // printk (BIOS_DEBUG, "%d: GAV: %x\n", line, in); |
| 148 | return in; |
| 149 | } |
| 150 | |
| 151 | #define gav(x) gav_real (__LINE__, (x)) |
Felix Held | 29a9c07 | 2018-07-29 01:34:45 +0200 | [diff] [blame] | 152 | |
Matthias Gazzari | dfa5125 | 2018-05-19 00:44:20 +0200 | [diff] [blame] | 153 | /* Global allocation of timings_car */ |
Arthur Heymans | 33ab29f | 2018-12-29 13:34:30 +0100 | [diff] [blame] | 154 | timing_bounds_t timings_car[64]; |
Matthias Gazzari | dfa5125 | 2018-05-19 00:44:20 +0200 | [diff] [blame] | 155 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 156 | /* OK */ |
| 157 | static u16 |
| 158 | read_500(struct raminfo *info, int channel, u16 addr, int split) |
| 159 | { |
| 160 | u32 val; |
| 161 | info->last_500_command[channel] = 0x80000000; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 162 | MCHBAR32(0x500 + (channel << 10)) = 0; |
| 163 | while (MCHBAR32(0x500 + (channel << 10)) & 0x800000) |
| 164 | ; |
| 165 | MCHBAR32(0x500 + (channel << 10)) = |
| 166 | 0x80000000 | (((MCHBAR8(0x246 + (channel << 10)) >> 2) & 3) |
| 167 | + 0xb88 - addr); |
| 168 | while (MCHBAR32(0x500 + (channel << 10)) & 0x800000) |
| 169 | ; |
| 170 | val = MCHBAR32(0x508 + (channel << 10)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 171 | return val & ((1 << split) - 1); |
| 172 | } |
| 173 | |
| 174 | /* OK */ |
| 175 | static void |
| 176 | write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, |
| 177 | int flag) |
| 178 | { |
| 179 | if (info->last_500_command[channel] == 0x80000000) { |
| 180 | info->last_500_command[channel] = 0x40000000; |
| 181 | write_500(info, channel, 0, 0xb61, 0, 0); |
| 182 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 183 | MCHBAR32(0x500 + (channel << 10)) = 0; |
| 184 | while (MCHBAR32(0x500 + (channel << 10)) & 0x800000) |
| 185 | ; |
| 186 | MCHBAR32(0x504 + (channel << 10)) = |
| 187 | (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits); |
| 188 | MCHBAR32(0x500 + (channel << 10)) = 0x40000000 | addr; |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 189 | while (MCHBAR32(0x500 + (channel << 10)) & 0x800000) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 190 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 191 | } |
| 192 | |
Angel Pons | c10f8b2 | 2021-01-15 20:34:51 +0100 | [diff] [blame] | 193 | static void rmw_500(struct raminfo *info, int channel, u16 addr, int bits, u32 and, u32 or) |
| 194 | { |
| 195 | const u32 val = read_500(info, channel, addr, bits) & and; |
| 196 | write_500(info, channel, val | or, addr, bits, 1); |
| 197 | } |
| 198 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 199 | static int rw_test(int rank) |
| 200 | { |
| 201 | const u32 mask = 0xf00fc33c; |
| 202 | int ok = 0xff; |
| 203 | int i; |
| 204 | for (i = 0; i < 64; i++) |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 205 | write32p((rank << 28) | (i << 2), 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 206 | sfence(); |
| 207 | for (i = 0; i < 64; i++) |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 208 | gav(read32p((rank << 28) | (i << 2))); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 209 | sfence(); |
| 210 | for (i = 0; i < 32; i++) { |
| 211 | u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 212 | write32p((rank << 28) | (i << 3), pat); |
| 213 | write32p((rank << 28) | (i << 3) | 4, pat); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 214 | } |
| 215 | sfence(); |
| 216 | for (i = 0; i < 32; i++) { |
| 217 | u8 pat = (((mask >> i) & 1) ? 0xff : 0); |
| 218 | int j; |
| 219 | u32 val; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 220 | gav(val = read32p((rank << 28) | (i << 3))); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 221 | for (j = 0; j < 4; j++) |
| 222 | if (((val >> (j * 8)) & 0xff) != pat) |
| 223 | ok &= ~(1 << j); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 224 | gav(val = read32p((rank << 28) | (i << 3) | 4)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 225 | for (j = 0; j < 4; j++) |
| 226 | if (((val >> (j * 8)) & 0xff) != pat) |
| 227 | ok &= ~(16 << j); |
| 228 | } |
| 229 | sfence(); |
| 230 | for (i = 0; i < 64; i++) |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 231 | write32p((rank << 28) | (i << 2), 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 232 | sfence(); |
| 233 | for (i = 0; i < 64; i++) |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 234 | gav(read32p((rank << 28) | (i << 2))); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 235 | |
| 236 | return ok; |
| 237 | } |
| 238 | |
| 239 | static void |
| 240 | program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank) |
| 241 | { |
| 242 | int lane; |
| 243 | for (lane = 0; lane < 8; lane++) { |
| 244 | write_500(info, channel, |
| 245 | base + |
| 246 | info->training. |
| 247 | lane_timings[2][channel][slot][rank][lane], |
| 248 | get_timing_register_addr(lane, 2, slot, rank), 9, 0); |
| 249 | write_500(info, channel, |
| 250 | base + |
| 251 | info->training. |
| 252 | lane_timings[3][channel][slot][rank][lane], |
| 253 | get_timing_register_addr(lane, 3, slot, rank), 9, 0); |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | static void write_26c(int channel, u16 si) |
| 258 | { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 259 | MCHBAR32(0x26c + (channel << 10)) = 0x03243f35; |
| 260 | MCHBAR32(0x268 + (channel << 10)) = 0xcfc00000 | (si << 9); |
| 261 | MCHBAR16(0x2b9 + (channel << 10)) = si; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 262 | } |
| 263 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 264 | static void toggle_1d0_142_5ff(void) |
| 265 | { |
| 266 | u32 reg32 = gav(read_1d0(0x142, 3)); |
| 267 | if (reg32 & (1 << 1)) |
| 268 | write_1d0(0, 0x142, 3, 1); |
| 269 | |
| 270 | MCHBAR8(0x5ff) = 0x0; |
| 271 | MCHBAR8(0x5ff) = 0x80; |
| 272 | if (reg32 & (1 << 1)) |
| 273 | write_1d0(0x2, 0x142, 3, 1); |
| 274 | } |
| 275 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 276 | static u32 get_580(int channel, u8 addr) |
| 277 | { |
| 278 | u32 ret; |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 279 | toggle_1d0_142_5ff(); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 280 | MCHBAR32(0x580 + (channel << 10)) = 0x8493c012 | addr; |
| 281 | MCHBAR8_OR(0x580 + (channel << 10), 1); |
| 282 | while (!((ret = MCHBAR32(0x580 + (channel << 10))) & 0x10000)) |
| 283 | ; |
| 284 | MCHBAR8_AND(0x580 + (channel << 10), ~1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 285 | return ret; |
| 286 | } |
| 287 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 288 | #define RANK_SHIFT 28 |
| 289 | #define CHANNEL_SHIFT 10 |
| 290 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 291 | static void seq9(struct raminfo *info, int channel, int slot, int rank) |
| 292 | { |
| 293 | int i, lane; |
| 294 | |
| 295 | for (i = 0; i < 2; i++) |
| 296 | for (lane = 0; lane < 8; lane++) |
| 297 | write_500(info, channel, |
| 298 | info->training.lane_timings[i + |
| 299 | 1][channel][slot] |
| 300 | [rank][lane], get_timing_register_addr(lane, |
| 301 | i + 1, |
| 302 | slot, |
| 303 | rank), |
| 304 | 9, 0); |
| 305 | |
| 306 | write_1d0(1, 0x103, 6, 1); |
| 307 | for (lane = 0; lane < 8; lane++) |
| 308 | write_500(info, channel, |
| 309 | info->training. |
| 310 | lane_timings[0][channel][slot][rank][lane], |
| 311 | get_timing_register_addr(lane, 0, slot, rank), 9, 0); |
| 312 | |
| 313 | for (i = 0; i < 2; i++) { |
| 314 | for (lane = 0; lane < 8; lane++) |
| 315 | write_500(info, channel, |
| 316 | info->training.lane_timings[i + |
| 317 | 1][channel][slot] |
| 318 | [rank][lane], get_timing_register_addr(lane, |
| 319 | i + 1, |
| 320 | slot, |
| 321 | rank), |
| 322 | 9, 0); |
| 323 | gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); |
| 324 | } |
| 325 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 326 | toggle_1d0_142_5ff(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 327 | write_1d0(0x2, 0x142, 3, 1); |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 328 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 329 | for (lane = 0; lane < 8; lane++) { |
| 330 | // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); |
| 331 | info->training.lane_timings[2][channel][slot][rank][lane] = |
| 332 | read_500(info, channel, |
| 333 | get_timing_register_addr(lane, 2, slot, rank), 9); |
| 334 | //printk (BIOS_ERR, "after: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); |
| 335 | info->training.lane_timings[3][channel][slot][rank][lane] = |
| 336 | info->training.lane_timings[2][channel][slot][rank][lane] + |
| 337 | 0x20; |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | static int count_ranks_in_channel(struct raminfo *info, int channel) |
| 342 | { |
| 343 | int slot, rank; |
| 344 | int res = 0; |
| 345 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 346 | for (rank = 0; rank < NUM_SLOTS; rank++) |
| 347 | res += info->populated_ranks[channel][slot][rank]; |
| 348 | return res; |
| 349 | } |
| 350 | |
| 351 | static void |
| 352 | config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank) |
| 353 | { |
| 354 | int add; |
| 355 | |
| 356 | write_1d0(0, 0x178, 7, 1); |
| 357 | seq9(info, channel, slot, rank); |
| 358 | program_timings(info, 0x80, channel, slot, rank); |
| 359 | |
| 360 | if (channel == 0) |
| 361 | add = count_ranks_in_channel(info, 1); |
| 362 | else |
| 363 | add = 0; |
| 364 | if (!s3resume) |
| 365 | gav(rw_test(rank + add)); |
| 366 | program_timings(info, 0x00, channel, slot, rank); |
| 367 | if (!s3resume) |
| 368 | gav(rw_test(rank + add)); |
| 369 | if (!s3resume) |
| 370 | gav(rw_test(rank + add)); |
| 371 | write_1d0(0, 0x142, 3, 1); |
| 372 | write_1d0(0, 0x103, 6, 1); |
| 373 | |
| 374 | gav(get_580(channel, 0xc | (rank << 5))); |
| 375 | gav(read_1d0(0x142, 3)); |
| 376 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 377 | MCHBAR8(0x5ff) = 0x0; |
| 378 | MCHBAR8(0x5ff) = 0x80; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 379 | } |
| 380 | |
Angel Pons | c10f8b2 | 2021-01-15 20:34:51 +0100 | [diff] [blame] | 381 | static void set_4cf(struct raminfo *info, int channel, u8 bit, u8 val) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 382 | { |
Angel Pons | c10f8b2 | 2021-01-15 20:34:51 +0100 | [diff] [blame] | 383 | const u16 regtable[] = { 0x4cf, 0x659, 0x697 }; |
| 384 | |
| 385 | val &= 1; |
| 386 | for (int i = 0; i < ARRAY_SIZE(regtable); i++) |
| 387 | rmw_500(info, channel, regtable[i], 4, ~(1 << bit), val << bit); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | static void set_334(int zero) |
| 391 | { |
| 392 | int j, k, channel; |
| 393 | const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b }; |
| 394 | u32 vd8[2][16]; |
| 395 | |
| 396 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 397 | for (j = 0; j < 4; j++) { |
| 398 | u32 a = (j == 1) ? 0x29292929 : 0x31313131; |
| 399 | u32 lmask = (j == 3) ? 0xffff : 0xffffffff; |
| 400 | u16 c; |
| 401 | if ((j == 0 || j == 3) && zero) |
| 402 | c = 0; |
| 403 | else if (j == 3) |
| 404 | c = 0x5f; |
| 405 | else |
| 406 | c = 0x5f5f; |
| 407 | |
| 408 | for (k = 0; k < 2; k++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 409 | MCHBAR32(0x138 + 8 * k) = |
| 410 | (channel << 26) | (j << 24); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 411 | gav(vd8[1][(channel << 3) | (j << 1) | k] = |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 412 | MCHBAR32(0x138 + 8 * k)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 413 | gav(vd8[0][(channel << 3) | (j << 1) | k] = |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 414 | MCHBAR32(0x13c + 8 * k)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 415 | } |
| 416 | |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 417 | MCHBAR32(0x334 + (channel << 10) + (j * 0x44)) = |
| 418 | zero ? 0 : val3[j]; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 419 | MCHBAR32(0x32c + (channel << 10) + (j * 0x44)) = |
| 420 | zero ? 0 : (0x18191819 & lmask); |
| 421 | MCHBAR16(0x34a + (channel << 10) + (j * 0x44)) = c; |
| 422 | MCHBAR32(0x33c + (channel << 10) + (j * 0x44)) = |
| 423 | zero ? 0 : (a & lmask); |
| 424 | MCHBAR32(0x344 + (channel << 10) + (j * 0x44)) = |
| 425 | zero ? 0 : (a & lmask); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 426 | } |
| 427 | } |
| 428 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 429 | MCHBAR32_OR(0x130, 1); |
| 430 | while (MCHBAR8(0x130) & 1) |
| 431 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 432 | } |
| 433 | |
Angel Pons | 244f455 | 2021-01-15 20:41:36 +0100 | [diff] [blame] | 434 | static void rmw_1d0(u16 addr, u32 and, u32 or, int split) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 435 | { |
| 436 | u32 v; |
| 437 | v = read_1d0(addr, split); |
Angel Pons | 244f455 | 2021-01-15 20:41:36 +0100 | [diff] [blame] | 438 | write_1d0((v & and) | or, addr, split, 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 439 | } |
| 440 | |
| 441 | static int find_highest_bit_set(u16 val) |
| 442 | { |
| 443 | int i; |
| 444 | for (i = 15; i >= 0; i--) |
| 445 | if (val & (1 << i)) |
| 446 | return i; |
| 447 | return -1; |
| 448 | } |
| 449 | |
| 450 | static int find_lowest_bit_set32(u32 val) |
| 451 | { |
| 452 | int i; |
| 453 | for (i = 0; i < 32; i++) |
| 454 | if (val & (1 << i)) |
| 455 | return i; |
| 456 | return -1; |
| 457 | } |
| 458 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 459 | enum { |
| 460 | DEVICE_TYPE = 2, |
| 461 | MODULE_TYPE = 3, |
| 462 | DENSITY = 4, |
| 463 | RANKS_AND_DQ = 7, |
| 464 | MEMORY_BUS_WIDTH = 8, |
| 465 | TIMEBASE_DIVIDEND = 10, |
| 466 | TIMEBASE_DIVISOR = 11, |
| 467 | CYCLETIME = 12, |
| 468 | |
| 469 | CAS_LATENCIES_LSB = 14, |
| 470 | CAS_LATENCIES_MSB = 15, |
| 471 | CAS_LATENCY_TIME = 16, |
| 472 | THERMAL_AND_REFRESH = 31, |
| 473 | REFERENCE_RAW_CARD_USED = 62, |
| 474 | RANK1_ADDRESS_MAPPING = 63 |
| 475 | }; |
| 476 | |
| 477 | static void calculate_timings(struct raminfo *info) |
| 478 | { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 479 | unsigned int cycletime; |
| 480 | unsigned int cas_latency_time; |
| 481 | unsigned int supported_cas_latencies; |
| 482 | unsigned int channel, slot; |
| 483 | unsigned int clock_speed_index; |
| 484 | unsigned int min_cas_latency; |
| 485 | unsigned int cas_latency; |
| 486 | unsigned int max_clock_index; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 487 | |
| 488 | /* Find common CAS latency */ |
| 489 | supported_cas_latencies = 0x3fe; |
| 490 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 491 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 492 | if (info->populated_ranks[channel][slot][0]) |
| 493 | supported_cas_latencies &= |
| 494 | 2 * |
| 495 | (info-> |
| 496 | spd[channel][slot][CAS_LATENCIES_LSB] | |
| 497 | (info-> |
| 498 | spd[channel][slot][CAS_LATENCIES_MSB] << |
| 499 | 8)); |
| 500 | |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 501 | max_clock_index = MIN(3, info->max_supported_clock_speed_index); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 502 | |
| 503 | cycletime = min_cycletime[max_clock_index]; |
| 504 | cas_latency_time = min_cas_latency_time[max_clock_index]; |
| 505 | |
| 506 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 507 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 508 | if (info->populated_ranks[channel][slot][0]) { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 509 | unsigned int timebase; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 510 | timebase = |
| 511 | 1000 * |
| 512 | info-> |
| 513 | spd[channel][slot][TIMEBASE_DIVIDEND] / |
| 514 | info->spd[channel][slot][TIMEBASE_DIVISOR]; |
| 515 | cycletime = |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 516 | MAX(cycletime, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 517 | timebase * |
| 518 | info->spd[channel][slot][CYCLETIME]); |
| 519 | cas_latency_time = |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 520 | MAX(cas_latency_time, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 521 | timebase * |
| 522 | info-> |
| 523 | spd[channel][slot][CAS_LATENCY_TIME]); |
| 524 | } |
Jacob Garber | 3c19382 | 2019-06-10 18:23:32 -0600 | [diff] [blame] | 525 | if (cycletime > min_cycletime[0]) |
| 526 | die("RAM init: Decoded SPD DRAM freq is slower than the controller minimum!"); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 527 | for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) { |
| 528 | if (cycletime == min_cycletime[clock_speed_index]) |
| 529 | break; |
| 530 | if (cycletime > min_cycletime[clock_speed_index]) { |
| 531 | clock_speed_index--; |
| 532 | cycletime = min_cycletime[clock_speed_index]; |
| 533 | break; |
| 534 | } |
| 535 | } |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 536 | min_cas_latency = DIV_ROUND_UP(cas_latency_time, cycletime); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 537 | cas_latency = 0; |
| 538 | while (supported_cas_latencies) { |
| 539 | cas_latency = find_highest_bit_set(supported_cas_latencies) + 3; |
| 540 | if (cas_latency <= min_cas_latency) |
| 541 | break; |
| 542 | supported_cas_latencies &= |
| 543 | ~(1 << find_highest_bit_set(supported_cas_latencies)); |
| 544 | } |
| 545 | |
| 546 | if (cas_latency != min_cas_latency && clock_speed_index) |
| 547 | clock_speed_index--; |
| 548 | |
| 549 | if (cas_latency * min_cycletime[clock_speed_index] > 20000) |
| 550 | die("Couldn't configure DRAM"); |
| 551 | info->clock_speed_index = clock_speed_index; |
| 552 | info->cas_latency = cas_latency; |
| 553 | } |
| 554 | |
| 555 | static void program_base_timings(struct raminfo *info) |
| 556 | { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 557 | unsigned int channel; |
| 558 | unsigned int slot, rank, lane; |
| 559 | unsigned int extended_silicon_revision; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 560 | int i; |
| 561 | |
| 562 | extended_silicon_revision = info->silicon_revision; |
| 563 | if (info->silicon_revision == 0) |
| 564 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 565 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 566 | if ((info-> |
| 567 | spd[channel][slot][MODULE_TYPE] & 0xF) == |
| 568 | 3) |
| 569 | extended_silicon_revision = 4; |
| 570 | |
| 571 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 572 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 573 | for (rank = 0; rank < NUM_SLOTS; rank++) { |
| 574 | int card_timing_2; |
| 575 | if (!info->populated_ranks[channel][slot][rank]) |
| 576 | continue; |
| 577 | |
| 578 | for (lane = 0; lane < 9; lane++) { |
| 579 | int tm_reg; |
| 580 | int card_timing; |
| 581 | |
| 582 | card_timing = 0; |
| 583 | if ((info-> |
| 584 | spd[channel][slot][MODULE_TYPE] & |
| 585 | 0xF) == 3) { |
| 586 | int reference_card; |
| 587 | reference_card = |
| 588 | info-> |
| 589 | spd[channel][slot] |
| 590 | [REFERENCE_RAW_CARD_USED] & |
| 591 | 0x1f; |
| 592 | if (reference_card == 3) |
| 593 | card_timing = |
| 594 | u16_ffd1188[0][lane] |
| 595 | [info-> |
| 596 | clock_speed_index]; |
| 597 | if (reference_card == 5) |
| 598 | card_timing = |
| 599 | u16_ffd1188[1][lane] |
| 600 | [info-> |
| 601 | clock_speed_index]; |
| 602 | } |
| 603 | |
| 604 | info->training. |
| 605 | lane_timings[0][channel][slot][rank] |
| 606 | [lane] = |
| 607 | u8_FFFD1218[info-> |
| 608 | clock_speed_index]; |
| 609 | info->training. |
| 610 | lane_timings[1][channel][slot][rank] |
| 611 | [lane] = 256; |
| 612 | |
| 613 | for (tm_reg = 2; tm_reg < 4; tm_reg++) |
| 614 | info->training. |
| 615 | lane_timings[tm_reg] |
| 616 | [channel][slot][rank][lane] |
| 617 | = |
| 618 | u8_FFFD1240[channel] |
| 619 | [extended_silicon_revision] |
| 620 | [lane][2 * slot + |
| 621 | rank][info-> |
| 622 | clock_speed_index] |
| 623 | + info->max4048[channel] |
| 624 | + |
| 625 | u8_FFFD0C78[channel] |
| 626 | [extended_silicon_revision] |
| 627 | [info-> |
| 628 | mode4030[channel]][slot] |
| 629 | [rank][info-> |
| 630 | clock_speed_index] |
| 631 | + card_timing; |
| 632 | for (tm_reg = 0; tm_reg < 4; tm_reg++) |
| 633 | write_500(info, channel, |
| 634 | info->training. |
| 635 | lane_timings[tm_reg] |
| 636 | [channel][slot][rank] |
| 637 | [lane], |
| 638 | get_timing_register_addr |
| 639 | (lane, tm_reg, slot, |
| 640 | rank), 9, 0); |
| 641 | } |
| 642 | |
| 643 | card_timing_2 = 0; |
| 644 | if (!(extended_silicon_revision != 4 |
| 645 | || (info-> |
| 646 | populated_ranks_mask[channel] & 5) == |
| 647 | 5)) { |
| 648 | if ((info-> |
| 649 | spd[channel][slot] |
| 650 | [REFERENCE_RAW_CARD_USED] & 0x1F) |
| 651 | == 3) |
| 652 | card_timing_2 = |
| 653 | u16_FFFE0EB8[0][info-> |
| 654 | clock_speed_index]; |
| 655 | if ((info-> |
| 656 | spd[channel][slot] |
| 657 | [REFERENCE_RAW_CARD_USED] & 0x1F) |
| 658 | == 5) |
| 659 | card_timing_2 = |
| 660 | u16_FFFE0EB8[1][info-> |
| 661 | clock_speed_index]; |
| 662 | } |
| 663 | |
| 664 | for (i = 0; i < 3; i++) |
| 665 | write_500(info, channel, |
| 666 | (card_timing_2 + |
| 667 | info->max4048[channel] |
| 668 | + |
| 669 | u8_FFFD0EF8[channel] |
| 670 | [extended_silicon_revision] |
| 671 | [info-> |
| 672 | mode4030[channel]][info-> |
| 673 | clock_speed_index]), |
| 674 | u16_fffd0c50[i][slot][rank], |
| 675 | 8, 1); |
| 676 | write_500(info, channel, |
| 677 | (info->max4048[channel] + |
| 678 | u8_FFFD0C78[channel] |
| 679 | [extended_silicon_revision][info-> |
| 680 | mode4030 |
| 681 | [channel]] |
| 682 | [slot][rank][info-> |
| 683 | clock_speed_index]), |
| 684 | u16_fffd0c70[slot][rank], 7, 1); |
| 685 | } |
| 686 | if (!info->populated_ranks_mask[channel]) |
| 687 | continue; |
| 688 | for (i = 0; i < 3; i++) |
| 689 | write_500(info, channel, |
| 690 | (info->max4048[channel] + |
| 691 | info->avg4044[channel] |
| 692 | + |
| 693 | u8_FFFD17E0[channel] |
| 694 | [extended_silicon_revision][info-> |
| 695 | mode4030 |
| 696 | [channel]][info-> |
| 697 | clock_speed_index]), |
| 698 | u16_fffd0c68[i], 8, 1); |
| 699 | } |
| 700 | } |
| 701 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 702 | /* The time of clock cycle in ps. */ |
| 703 | static unsigned int cycle_ps(struct raminfo *info) |
| 704 | { |
| 705 | return 2 * halfcycle_ps(info); |
| 706 | } |
| 707 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 708 | /* Frequency in 0.1 MHz units. */ |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 709 | static unsigned int frequency_01(struct raminfo *info) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 710 | { |
| 711 | return 100 * frequency_11(info) / 9; |
| 712 | } |
| 713 | |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 714 | static unsigned int ps_to_halfcycles(struct raminfo *info, unsigned int ps) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 715 | { |
| 716 | return (frequency_11(info) * 2) * ps / 900000; |
| 717 | } |
| 718 | |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 719 | static unsigned int ns_to_cycles(struct raminfo *info, unsigned int ns) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 720 | { |
| 721 | return (frequency_11(info)) * ns / 900; |
| 722 | } |
| 723 | |
| 724 | static void compute_derived_timings(struct raminfo *info) |
| 725 | { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 726 | unsigned int channel, slot, rank; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 727 | int extended_silicon_revision; |
| 728 | int some_delay_1_ps; |
| 729 | int some_delay_2_ps; |
| 730 | int some_delay_2_halfcycles_ceil; |
| 731 | int some_delay_2_halfcycles_floor; |
| 732 | int some_delay_3_ps; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 733 | int some_delay_3_ps_rounded; |
| 734 | int some_delay_1_cycle_ceil; |
| 735 | int some_delay_1_cycle_floor; |
| 736 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 737 | some_delay_3_ps_rounded = 0; |
| 738 | extended_silicon_revision = info->silicon_revision; |
| 739 | if (!info->silicon_revision) |
| 740 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 741 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 742 | if ((info-> |
| 743 | spd[channel][slot][MODULE_TYPE] & 0xF) == |
| 744 | 3) |
| 745 | extended_silicon_revision = 4; |
| 746 | if (info->board_lane_delay[7] < 5) |
| 747 | info->board_lane_delay[7] = 5; |
| 748 | info->revision_flag_1 = 2; |
| 749 | if (info->silicon_revision == 2 || info->silicon_revision == 3) |
| 750 | info->revision_flag_1 = 0; |
| 751 | if (info->revision < 16) |
| 752 | info->revision_flag_1 = 0; |
| 753 | |
| 754 | if (info->revision < 8) |
| 755 | info->revision_flag_1 = 0; |
| 756 | if (info->revision >= 8 && (info->silicon_revision == 0 |
| 757 | || info->silicon_revision == 1)) |
| 758 | some_delay_2_ps = 735; |
| 759 | else |
| 760 | some_delay_2_ps = 750; |
| 761 | |
| 762 | if (info->revision >= 0x10 && (info->silicon_revision == 0 |
| 763 | || info->silicon_revision == 1)) |
| 764 | some_delay_1_ps = 3929; |
| 765 | else |
| 766 | some_delay_1_ps = 3490; |
| 767 | |
| 768 | some_delay_1_cycle_floor = some_delay_1_ps / cycle_ps(info); |
| 769 | some_delay_1_cycle_ceil = some_delay_1_ps / cycle_ps(info); |
| 770 | if (some_delay_1_ps % cycle_ps(info)) |
| 771 | some_delay_1_cycle_ceil++; |
| 772 | else |
| 773 | some_delay_1_cycle_floor--; |
| 774 | info->some_delay_1_cycle_floor = some_delay_1_cycle_floor; |
| 775 | if (info->revision_flag_1) |
| 776 | some_delay_2_ps = halfcycle_ps(info) >> 6; |
| 777 | some_delay_2_ps += |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 778 | MAX(some_delay_1_ps - 30, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 779 | 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + |
| 780 | 375; |
| 781 | some_delay_3_ps = |
| 782 | halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info); |
| 783 | if (info->revision_flag_1) { |
Elyes HAOUAS | 6f7c955 | 2019-10-18 20:20:03 +0200 | [diff] [blame] | 784 | if (some_delay_3_ps >= 150) { |
| 785 | const int some_delay_3_halfcycles = |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 786 | (some_delay_3_ps << 6) / halfcycle_ps(info); |
Elyes HAOUAS | 6f7c955 | 2019-10-18 20:20:03 +0200 | [diff] [blame] | 787 | some_delay_3_ps_rounded = |
| 788 | halfcycle_ps(info) * some_delay_3_halfcycles >> 6; |
| 789 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 790 | } |
| 791 | some_delay_2_halfcycles_ceil = |
| 792 | (some_delay_2_ps + halfcycle_ps(info) - 1) / halfcycle_ps(info) - |
| 793 | 2 * (some_delay_1_cycle_ceil - 1); |
| 794 | if (info->revision_flag_1 && some_delay_3_ps < 150) |
| 795 | some_delay_2_halfcycles_ceil++; |
| 796 | some_delay_2_halfcycles_floor = some_delay_2_halfcycles_ceil; |
| 797 | if (info->revision < 0x10) |
| 798 | some_delay_2_halfcycles_floor = |
| 799 | some_delay_2_halfcycles_ceil - 1; |
| 800 | if (!info->revision_flag_1) |
| 801 | some_delay_2_halfcycles_floor++; |
| 802 | info->some_delay_2_halfcycles_ceil = some_delay_2_halfcycles_ceil; |
| 803 | info->some_delay_3_ps_rounded = some_delay_3_ps_rounded; |
| 804 | if ((info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0]) |
| 805 | || (info->populated_ranks[1][0][0] |
| 806 | && info->populated_ranks[1][1][0])) |
| 807 | info->max_slots_used_in_channel = 2; |
| 808 | else |
| 809 | info->max_slots_used_in_channel = 1; |
| 810 | for (channel = 0; channel < 2; channel++) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 811 | MCHBAR32(0x244 + (channel << 10)) = |
| 812 | ((info->revision < 8) ? 1 : 0x200) | |
| 813 | ((2 - info->max_slots_used_in_channel) << 17) | |
| 814 | (channel << 21) | |
| 815 | (info->some_delay_1_cycle_floor << 18) | 0x9510; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 816 | if (info->max_slots_used_in_channel == 1) { |
| 817 | info->mode4030[0] = (count_ranks_in_channel(info, 0) == 2); |
| 818 | info->mode4030[1] = (count_ranks_in_channel(info, 1) == 2); |
| 819 | } else { |
| 820 | info->mode4030[0] = ((count_ranks_in_channel(info, 0) == 1) || (count_ranks_in_channel(info, 0) == 2)) ? 2 : 3; /* 2 if 1 or 2 ranks */ |
| 821 | info->mode4030[1] = ((count_ranks_in_channel(info, 1) == 1) |
| 822 | || (count_ranks_in_channel(info, 1) == |
| 823 | 2)) ? 2 : 3; |
| 824 | } |
| 825 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 826 | int max_of_unk; |
| 827 | int min_of_unk_2; |
| 828 | |
| 829 | int i, count; |
| 830 | int sum; |
| 831 | |
| 832 | if (!info->populated_ranks_mask[channel]) |
| 833 | continue; |
| 834 | |
| 835 | max_of_unk = 0; |
| 836 | min_of_unk_2 = 32767; |
| 837 | |
| 838 | sum = 0; |
| 839 | count = 0; |
| 840 | for (i = 0; i < 3; i++) { |
| 841 | int unk1; |
| 842 | if (info->revision < 8) |
| 843 | unk1 = |
| 844 | u8_FFFD1891[0][channel][info-> |
| 845 | clock_speed_index] |
| 846 | [i]; |
| 847 | else if (! |
| 848 | (info->revision >= 0x10 |
| 849 | || info->revision_flag_1)) |
| 850 | unk1 = |
| 851 | u8_FFFD1891[1][channel][info-> |
| 852 | clock_speed_index] |
| 853 | [i]; |
| 854 | else |
| 855 | unk1 = 0; |
| 856 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 857 | for (rank = 0; rank < NUM_RANKS; rank++) { |
| 858 | int a = 0; |
| 859 | int b = 0; |
| 860 | |
| 861 | if (!info-> |
| 862 | populated_ranks[channel][slot] |
| 863 | [rank]) |
| 864 | continue; |
| 865 | if (extended_silicon_revision == 4 |
| 866 | && (info-> |
| 867 | populated_ranks_mask[channel] & |
| 868 | 5) != 5) { |
| 869 | if ((info-> |
| 870 | spd[channel][slot] |
| 871 | [REFERENCE_RAW_CARD_USED] & |
| 872 | 0x1F) == 3) { |
| 873 | a = u16_ffd1178[0] |
| 874 | [info-> |
| 875 | clock_speed_index]; |
| 876 | b = u16_fe0eb8[0][info-> |
| 877 | clock_speed_index]; |
| 878 | } else |
| 879 | if ((info-> |
| 880 | spd[channel][slot] |
| 881 | [REFERENCE_RAW_CARD_USED] |
| 882 | & 0x1F) == 5) { |
| 883 | a = u16_ffd1178[1] |
| 884 | [info-> |
| 885 | clock_speed_index]; |
| 886 | b = u16_fe0eb8[1][info-> |
| 887 | clock_speed_index]; |
| 888 | } |
| 889 | } |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 890 | min_of_unk_2 = MIN(min_of_unk_2, a); |
| 891 | min_of_unk_2 = MIN(min_of_unk_2, b); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 892 | if (rank == 0) { |
| 893 | sum += a; |
| 894 | count++; |
| 895 | } |
| 896 | { |
| 897 | int t; |
| 898 | t = b + |
| 899 | u8_FFFD0EF8[channel] |
| 900 | [extended_silicon_revision] |
| 901 | [info-> |
| 902 | mode4030[channel]][info-> |
| 903 | clock_speed_index]; |
| 904 | if (unk1 >= t) |
| 905 | max_of_unk = |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 906 | MAX(max_of_unk, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 907 | unk1 - t); |
| 908 | } |
| 909 | } |
| 910 | { |
| 911 | int t = |
| 912 | u8_FFFD17E0[channel] |
| 913 | [extended_silicon_revision][info-> |
| 914 | mode4030 |
| 915 | [channel]] |
| 916 | [info->clock_speed_index] + min_of_unk_2; |
| 917 | if (unk1 >= t) |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 918 | max_of_unk = MAX(max_of_unk, unk1 - t); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 919 | } |
| 920 | } |
| 921 | |
Jacob Garber | 64fb4a3 | 2019-06-10 17:29:18 -0600 | [diff] [blame] | 922 | if (count == 0) |
| 923 | die("No memory ranks found for channel %u\n", channel); |
| 924 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 925 | info->avg4044[channel] = sum / count; |
| 926 | info->max4048[channel] = max_of_unk; |
| 927 | } |
| 928 | } |
| 929 | |
| 930 | static void jedec_read(struct raminfo *info, |
| 931 | int channel, int slot, int rank, |
| 932 | int total_rank, u8 addr3, unsigned int value) |
| 933 | { |
| 934 | /* Handle mirrored mapping. */ |
| 935 | if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 936 | addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | |
| 937 | ((addr3 >> 1) & 0x10); |
| 938 | MCHBAR8(0x271) = addr3 | (MCHBAR8(0x271) & 0xC1); |
| 939 | MCHBAR8(0x671) = addr3 | (MCHBAR8(0x671) & 0xC1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 940 | |
| 941 | /* Handle mirrored mapping. */ |
| 942 | if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) |
| 943 | value = |
| 944 | (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8) |
| 945 | << 1); |
| 946 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 947 | read32p((value << 3) | (total_rank << 28)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 948 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 949 | MCHBAR8(0x271) = (MCHBAR8(0x271) & 0xC3) | 2; |
| 950 | MCHBAR8(0x671) = (MCHBAR8(0x671) & 0xC3) | 2; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 951 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 952 | read32p(total_rank << 28); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 953 | } |
| 954 | |
| 955 | enum { |
| 956 | MR1_RZQ12 = 512, |
| 957 | MR1_RZQ2 = 64, |
| 958 | MR1_RZQ4 = 4, |
| 959 | MR1_ODS34OHM = 2 |
| 960 | }; |
| 961 | |
| 962 | enum { |
| 963 | MR0_BT_INTERLEAVED = 8, |
| 964 | MR0_DLL_RESET_ON = 256 |
| 965 | }; |
| 966 | |
| 967 | enum { |
| 968 | MR2_RTT_WR_DISABLED = 0, |
| 969 | MR2_RZQ2 = 1 << 10 |
| 970 | }; |
| 971 | |
| 972 | static void jedec_init(struct raminfo *info) |
| 973 | { |
| 974 | int write_recovery; |
| 975 | int channel, slot, rank; |
| 976 | int total_rank; |
| 977 | int dll_on; |
| 978 | int self_refresh_temperature; |
| 979 | int auto_self_refresh; |
| 980 | |
| 981 | auto_self_refresh = 1; |
| 982 | self_refresh_temperature = 1; |
| 983 | if (info->board_lane_delay[3] <= 10) { |
| 984 | if (info->board_lane_delay[3] <= 8) |
| 985 | write_recovery = info->board_lane_delay[3] - 4; |
| 986 | else |
| 987 | write_recovery = 5; |
| 988 | } else { |
| 989 | write_recovery = 6; |
| 990 | } |
| 991 | FOR_POPULATED_RANKS { |
| 992 | auto_self_refresh &= |
| 993 | (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1; |
| 994 | self_refresh_temperature &= |
| 995 | info->spd[channel][slot][THERMAL_AND_REFRESH] & 1; |
| 996 | } |
| 997 | if (auto_self_refresh == 1) |
| 998 | self_refresh_temperature = 0; |
| 999 | |
| 1000 | dll_on = ((info->silicon_revision != 2 && info->silicon_revision != 3) |
| 1001 | || (info->populated_ranks[0][0][0] |
| 1002 | && info->populated_ranks[0][1][0]) |
| 1003 | || (info->populated_ranks[1][0][0] |
| 1004 | && info->populated_ranks[1][1][0])); |
| 1005 | |
| 1006 | total_rank = 0; |
| 1007 | |
| 1008 | for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) { |
| 1009 | int rtt, rtt_wr = MR2_RTT_WR_DISABLED; |
| 1010 | int rzq_reg58e; |
| 1011 | |
| 1012 | if (info->silicon_revision == 2 || info->silicon_revision == 3) { |
| 1013 | rzq_reg58e = 64; |
| 1014 | rtt = MR1_RZQ2; |
| 1015 | if (info->clock_speed_index != 0) { |
| 1016 | rzq_reg58e = 4; |
| 1017 | if (info->populated_ranks_mask[channel] == 3) |
| 1018 | rtt = MR1_RZQ4; |
| 1019 | } |
| 1020 | } else { |
| 1021 | if ((info->populated_ranks_mask[channel] & 5) == 5) { |
| 1022 | rtt = MR1_RZQ12; |
| 1023 | rzq_reg58e = 64; |
| 1024 | rtt_wr = MR2_RZQ2; |
| 1025 | } else { |
| 1026 | rzq_reg58e = 4; |
| 1027 | rtt = MR1_RZQ4; |
| 1028 | } |
| 1029 | } |
| 1030 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1031 | MCHBAR16(0x588 + (channel << 10)) = 0x0; |
| 1032 | MCHBAR16(0x58a + (channel << 10)) = 0x4; |
| 1033 | MCHBAR16(0x58c + (channel << 10)) = rtt | MR1_ODS34OHM; |
| 1034 | MCHBAR16(0x58e + (channel << 10)) = rzq_reg58e | 0x82; |
| 1035 | MCHBAR16(0x590 + (channel << 10)) = 0x1282; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1036 | |
| 1037 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 1038 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 1039 | if (info->populated_ranks[channel][slot][rank]) { |
| 1040 | jedec_read(info, channel, slot, rank, |
| 1041 | total_rank, 0x28, |
| 1042 | rtt_wr | (info-> |
| 1043 | clock_speed_index |
| 1044 | << 3) |
| 1045 | | (auto_self_refresh << 6) | |
| 1046 | (self_refresh_temperature << |
| 1047 | 7)); |
| 1048 | jedec_read(info, channel, slot, rank, |
| 1049 | total_rank, 0x38, 0); |
| 1050 | jedec_read(info, channel, slot, rank, |
| 1051 | total_rank, 0x18, |
| 1052 | rtt | MR1_ODS34OHM); |
| 1053 | jedec_read(info, channel, slot, rank, |
| 1054 | total_rank, 6, |
| 1055 | (dll_on << 12) | |
| 1056 | (write_recovery << 9) |
| 1057 | | ((info->cas_latency - 4) << |
| 1058 | 4) | MR0_BT_INTERLEAVED | |
| 1059 | MR0_DLL_RESET_ON); |
| 1060 | total_rank++; |
| 1061 | } |
| 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | static void program_modules_memory_map(struct raminfo *info, int pre_jedec) |
| 1066 | { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 1067 | unsigned int channel, slot, rank; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1068 | unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ |
| 1069 | unsigned int channel_0_non_interleaved; |
| 1070 | |
| 1071 | FOR_ALL_RANKS { |
| 1072 | if (info->populated_ranks[channel][slot][rank]) { |
| 1073 | total_mb[channel] += |
| 1074 | pre_jedec ? 256 : (256 << info-> |
| 1075 | density[channel][slot] >> info-> |
| 1076 | is_x16_module[channel][slot]); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1077 | MCHBAR8(0x208 + rank + 2 * slot + (channel << 10)) = |
| 1078 | (pre_jedec ? (1 | ((1 + 1) << 1)) : |
| 1079 | (info->is_x16_module[channel][slot] | |
| 1080 | ((info->density[channel][slot] + 1) << 1))) | |
| 1081 | 0x80; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1082 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1083 | MCHBAR16(0x200 + (channel << 10) + 4 * slot + 2 * rank) = |
| 1084 | total_mb[channel] >> 6; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1085 | } |
| 1086 | |
| 1087 | info->total_memory_mb = total_mb[0] + total_mb[1]; |
| 1088 | |
| 1089 | info->interleaved_part_mb = |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 1090 | pre_jedec ? 0 : 2 * MIN(total_mb[0], total_mb[1]); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1091 | info->non_interleaved_part_mb = |
| 1092 | total_mb[0] + total_mb[1] - info->interleaved_part_mb; |
| 1093 | channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1094 | MCHBAR32(0x100) = channel_0_non_interleaved | |
| 1095 | (info->non_interleaved_part_mb << 16); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1096 | if (!pre_jedec) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1097 | MCHBAR16(0x104) = info->interleaved_part_mb; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1098 | } |
| 1099 | |
| 1100 | static void program_board_delay(struct raminfo *info) |
| 1101 | { |
| 1102 | int cas_latency_shift; |
| 1103 | int some_delay_ns; |
| 1104 | int some_delay_3_half_cycles; |
| 1105 | |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 1106 | unsigned int channel, i; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1107 | int high_multiplier; |
| 1108 | int lane_3_delay; |
| 1109 | int cas_latency_derived; |
| 1110 | |
| 1111 | high_multiplier = 0; |
| 1112 | some_delay_ns = 200; |
| 1113 | some_delay_3_half_cycles = 4; |
| 1114 | cas_latency_shift = info->silicon_revision == 0 |
| 1115 | || info->silicon_revision == 1 ? 1 : 0; |
| 1116 | if (info->revision < 8) { |
| 1117 | some_delay_ns = 600; |
| 1118 | cas_latency_shift = 0; |
| 1119 | } |
| 1120 | { |
| 1121 | int speed_bit; |
| 1122 | speed_bit = |
| 1123 | ((info->clock_speed_index > 1 |
| 1124 | || (info->silicon_revision != 2 |
| 1125 | && info->silicon_revision != 3))) ^ (info->revision >= |
| 1126 | 0x10); |
| 1127 | write_500(info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e, |
| 1128 | 3, 1); |
| 1129 | write_500(info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e, |
| 1130 | 3, 1); |
| 1131 | if (info->revision >= 0x10 && info->clock_speed_index <= 1 |
| 1132 | && (info->silicon_revision == 2 |
| 1133 | || info->silicon_revision == 3)) |
Angel Pons | 244f455 | 2021-01-15 20:41:36 +0100 | [diff] [blame] | 1134 | rmw_1d0(0x116, 5, 2, 4); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1135 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1136 | MCHBAR32(0x120) = (1 << (info->max_slots_used_in_channel + 28)) | |
| 1137 | 0x188e7f9f; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1138 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1139 | MCHBAR8(0x124) = info->board_lane_delay[4] + |
| 1140 | ((frequency_01(info) + 999) / 1000); |
| 1141 | MCHBAR16(0x125) = 0x1360; |
| 1142 | MCHBAR8(0x127) = 0x40; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1143 | if (info->fsb_frequency < frequency_11(info) / 2) { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 1144 | unsigned int some_delay_2_half_cycles; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1145 | high_multiplier = 1; |
| 1146 | some_delay_2_half_cycles = ps_to_halfcycles(info, |
| 1147 | ((3 * |
| 1148 | fsbcycle_ps(info)) |
| 1149 | >> 1) + |
| 1150 | (halfcycle_ps(info) |
| 1151 | * |
| 1152 | reg178_min[info-> |
| 1153 | clock_speed_index] |
| 1154 | >> 6) |
| 1155 | + |
| 1156 | 4 * |
| 1157 | halfcycle_ps(info) |
| 1158 | + 2230); |
| 1159 | some_delay_3_half_cycles = |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 1160 | MIN((some_delay_2_half_cycles + |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1161 | (frequency_11(info) * 2) * (28 - |
| 1162 | some_delay_2_half_cycles) / |
| 1163 | (frequency_11(info) * 2 - |
| 1164 | 4 * (info->fsb_frequency))) >> 3, 7); |
| 1165 | } |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 1166 | if (MCHBAR8(0x2ca9) & 1) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1167 | some_delay_3_half_cycles = 3; |
| 1168 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1169 | MCHBAR32_OR(0x220 + (channel << 10), 0x18001117); |
| 1170 | MCHBAR32(0x224 + (channel << 10)) = |
| 1171 | (info->max_slots_used_in_channel - 1) | |
| 1172 | ((info->cas_latency - 5 - info->clock_speed_index) |
| 1173 | << 21) | ((info->max_slots_used_in_channel + |
| 1174 | info->cas_latency - cas_latency_shift - 4) << 16) | |
| 1175 | ((info->cas_latency - cas_latency_shift - 4) << 26) | |
| 1176 | ((info->cas_latency - info->clock_speed_index + |
| 1177 | info->max_slots_used_in_channel - 6) << 8); |
| 1178 | MCHBAR32(0x228 + (channel << 10)) = |
| 1179 | info->max_slots_used_in_channel; |
| 1180 | MCHBAR8(0x239 + (channel << 10)) = 32; |
| 1181 | MCHBAR32(0x248 + (channel << 10)) = (high_multiplier << 24) | |
| 1182 | (some_delay_3_half_cycles << 25) | 0x840000; |
| 1183 | MCHBAR32(0x278 + (channel << 10)) = 0xc362042; |
| 1184 | MCHBAR32(0x27c + (channel << 10)) = 0x8b000062; |
| 1185 | MCHBAR32(0x24c + (channel << 10)) = |
| 1186 | ((!!info->clock_speed_index) << 17) | |
| 1187 | (((2 + info->clock_speed_index - |
| 1188 | (!!info->clock_speed_index))) << 12) | 0x10200; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1189 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1190 | MCHBAR8(0x267 + (channel << 10)) = 0x4; |
| 1191 | MCHBAR16(0x272 + (channel << 10)) = 0x155; |
| 1192 | MCHBAR32_AND_OR(0x2bc + (channel << 10), 0xFF000000, 0x707070); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1193 | |
| 1194 | write_500(info, channel, |
| 1195 | ((!info->populated_ranks[channel][1][1]) |
| 1196 | | (!info->populated_ranks[channel][1][0] << 1) |
| 1197 | | (!info->populated_ranks[channel][0][1] << 2) |
| 1198 | | (!info->populated_ranks[channel][0][0] << 3)), |
| 1199 | 0x4c9, 4, 1); |
| 1200 | } |
| 1201 | |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 1202 | MCHBAR8(0x2c4) = ((1 + (info->clock_speed_index != 0)) << 6) | 0xC; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1203 | { |
| 1204 | u8 freq_divisor = 2; |
| 1205 | if (info->fsb_frequency == frequency_11(info)) |
| 1206 | freq_divisor = 3; |
| 1207 | else if (2 * info->fsb_frequency < 3 * (frequency_11(info) / 2)) |
| 1208 | freq_divisor = 1; |
| 1209 | else |
| 1210 | freq_divisor = 2; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1211 | MCHBAR32(0x2c0) = (freq_divisor << 11) | 0x6009c400; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1212 | } |
| 1213 | |
| 1214 | if (info->board_lane_delay[3] <= 10) { |
| 1215 | if (info->board_lane_delay[3] <= 8) |
| 1216 | lane_3_delay = info->board_lane_delay[3]; |
| 1217 | else |
| 1218 | lane_3_delay = 10; |
| 1219 | } else { |
| 1220 | lane_3_delay = 12; |
| 1221 | } |
| 1222 | cas_latency_derived = info->cas_latency - info->clock_speed_index + 2; |
| 1223 | if (info->clock_speed_index > 1) |
| 1224 | cas_latency_derived++; |
| 1225 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1226 | MCHBAR32(0x240 + (channel << 10)) = |
| 1227 | ((info->clock_speed_index == 0) * 0x11000) | |
| 1228 | 0x1002100 | ((2 + info->clock_speed_index) << 4) | |
| 1229 | (info->cas_latency - 3); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1230 | write_500(info, channel, (info->clock_speed_index << 1) | 1, |
| 1231 | 0x609, 6, 1); |
| 1232 | write_500(info, channel, |
| 1233 | info->clock_speed_index + 2 * info->cas_latency - 7, |
| 1234 | 0x601, 6, 1); |
| 1235 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1236 | MCHBAR32(0x250 + (channel << 10)) = |
| 1237 | ((lane_3_delay + info->clock_speed_index + 9) << 6) | |
| 1238 | (info->board_lane_delay[7] << 2) | |
| 1239 | (info->board_lane_delay[4] << 16) | |
| 1240 | (info->board_lane_delay[1] << 25) | |
| 1241 | (info->board_lane_delay[1] << 29) | 1; |
| 1242 | MCHBAR32(0x254 + (channel << 10)) = |
| 1243 | (info->board_lane_delay[1] >> 3) | |
| 1244 | ((info->board_lane_delay[8] + 4 * info->use_ecc) << 6) | |
| 1245 | 0x80 | (info->board_lane_delay[6] << 1) | |
| 1246 | (info->board_lane_delay[2] << 28) | |
| 1247 | (cas_latency_derived << 16) | 0x4700000; |
| 1248 | MCHBAR32(0x258 + (channel << 10)) = |
| 1249 | ((info->board_lane_delay[5] + info->clock_speed_index + |
| 1250 | 9) << 12) | ((info->clock_speed_index - |
| 1251 | info->cas_latency + 12) << 8) | |
| 1252 | (info->board_lane_delay[2] << 17) | |
| 1253 | (info->board_lane_delay[4] << 24) | 0x47; |
| 1254 | MCHBAR32(0x25c + (channel << 10)) = |
| 1255 | (info->board_lane_delay[1] << 1) | |
| 1256 | (info->board_lane_delay[0] << 8) | 0x1da50000; |
| 1257 | MCHBAR8(0x264 + (channel << 10)) = 0xff; |
| 1258 | MCHBAR8(0x5f8 + (channel << 10)) = |
| 1259 | (cas_latency_shift << 3) | info->use_ecc; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1260 | } |
| 1261 | |
| 1262 | program_modules_memory_map(info, 1); |
| 1263 | |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 1264 | MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1265 | | (MCHBAR16(0x610) & 0x1C3) | 0x3C; |
| 1266 | MCHBAR16_OR(0x612, 0x100); |
| 1267 | MCHBAR16_OR(0x214, 0x3E00); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1268 | for (i = 0; i < 8; i++) { |
Angel Pons | 6757337 | 2020-07-22 16:56:00 +0200 | [diff] [blame] | 1269 | pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1270 | (info->total_memory_mb - 64) | !i | 2); |
Angel Pons | 6757337 | 2020-07-22 16:56:00 +0200 | [diff] [blame] | 1271 | pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1272 | } |
| 1273 | } |
| 1274 | |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1275 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 1276 | #define HOST_BRIDGE PCI_DEVFN(0, 0) |
| 1277 | |
| 1278 | static unsigned int get_mmio_size(void) |
| 1279 | { |
| 1280 | const struct device *dev; |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 1281 | const struct northbridge_intel_ironlake_config *cfg = NULL; |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1282 | |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 1283 | dev = pcidev_path_on_root(HOST_BRIDGE); |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1284 | if (dev) |
| 1285 | cfg = dev->chip_info; |
| 1286 | |
| 1287 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 1288 | if (!cfg || cfg->pci_mmio_size == 0) |
| 1289 | return DEFAULT_PCI_MMIO_SIZE; |
| 1290 | else |
| 1291 | return cfg->pci_mmio_size; |
| 1292 | } |
| 1293 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1294 | static void program_total_memory_map(struct raminfo *info) |
| 1295 | { |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1296 | unsigned int tom, tolud, touud; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1297 | unsigned int quickpath_reserved; |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1298 | unsigned int remap_base; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1299 | unsigned int uma_base_igd; |
| 1300 | unsigned int uma_base_gtt; |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1301 | unsigned int mmio_size; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1302 | int memory_remap; |
| 1303 | unsigned int memory_map[8]; |
| 1304 | int i; |
| 1305 | unsigned int current_limit; |
| 1306 | unsigned int tseg_base; |
| 1307 | int uma_size_igd = 0, uma_size_gtt = 0; |
| 1308 | |
| 1309 | memset(memory_map, 0, sizeof(memory_map)); |
| 1310 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1311 | if (info->uma_enabled) { |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 1312 | u16 t = pci_read_config16(NORTHBRIDGE, GGC); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1313 | gav(t); |
| 1314 | const int uma_sizes_gtt[16] = |
| 1315 | { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; |
| 1316 | /* Igd memory */ |
| 1317 | const int uma_sizes_igd[16] = { |
| 1318 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, |
| 1319 | 256, 512 |
| 1320 | }; |
| 1321 | |
| 1322 | uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF]; |
| 1323 | uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; |
| 1324 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1325 | |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1326 | mmio_size = get_mmio_size(); |
| 1327 | |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1328 | tom = info->total_memory_mb; |
| 1329 | if (tom == 4096) |
| 1330 | tom = 4032; |
| 1331 | touud = ALIGN_DOWN(tom - info->memory_reserved_for_heci_mb, 64); |
| 1332 | tolud = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) |
| 1333 | , touud), 64); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1334 | memory_remap = 0; |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1335 | if (touud - tolud > 64) { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1336 | memory_remap = 1; |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1337 | remap_base = MAX(4096, touud); |
| 1338 | touud = touud - tolud + 4096; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1339 | } |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1340 | if (touud > 4096) |
| 1341 | memory_map[2] = touud | 1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1342 | quickpath_reserved = 0; |
| 1343 | |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 1344 | u32 t = pci_read_config32(QPI_SAD, 0x68); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1345 | |
Jacob Garber | 975a7e3 | 2019-06-10 16:32:47 -0600 | [diff] [blame] | 1346 | gav(t); |
| 1347 | |
| 1348 | if (t & 0x800) { |
| 1349 | u32 shift = t >> 20; |
| 1350 | if (shift == 0) |
| 1351 | die("Quickpath value is 0\n"); |
| 1352 | quickpath_reserved = (u32)1 << find_lowest_bit_set32(shift); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1353 | } |
Jacob Garber | 975a7e3 | 2019-06-10 16:32:47 -0600 | [diff] [blame] | 1354 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1355 | if (memory_remap) |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1356 | touud -= quickpath_reserved; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1357 | |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 1358 | uma_base_igd = tolud - uma_size_igd; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1359 | uma_base_gtt = uma_base_igd - uma_size_gtt; |
| 1360 | tseg_base = ALIGN_DOWN(uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20); |
| 1361 | if (!memory_remap) |
| 1362 | tseg_base -= quickpath_reserved; |
| 1363 | tseg_base = ALIGN_DOWN(tseg_base, 8); |
| 1364 | |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 1365 | pci_write_config16(NORTHBRIDGE, TOLUD, tolud << 4); |
| 1366 | pci_write_config16(NORTHBRIDGE, TOM, tom >> 6); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1367 | if (memory_remap) { |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 1368 | pci_write_config16(NORTHBRIDGE, REMAPBASE, remap_base >> 6); |
| 1369 | pci_write_config16(NORTHBRIDGE, REMAPLIMIT, (touud - 64) >> 6); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1370 | } |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 1371 | pci_write_config16(NORTHBRIDGE, TOUUD, touud); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1372 | |
| 1373 | if (info->uma_enabled) { |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 1374 | pci_write_config32(NORTHBRIDGE, IGD_BASE, uma_base_igd << 20); |
| 1375 | pci_write_config32(NORTHBRIDGE, GTT_BASE, uma_base_gtt << 20); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1376 | } |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 1377 | pci_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1378 | |
| 1379 | current_limit = 0; |
| 1380 | memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1; |
| 1381 | memory_map[1] = 4096; |
| 1382 | for (i = 0; i < ARRAY_SIZE(memory_map); i++) { |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 1383 | current_limit = MAX(current_limit, memory_map[i] & ~1); |
Angel Pons | 6757337 | 2020-07-22 16:56:00 +0200 | [diff] [blame] | 1384 | pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1385 | (memory_map[i] & 1) | ALIGN_DOWN(current_limit - |
| 1386 | 1, 64) | 2); |
Angel Pons | 6757337 | 2020-07-22 16:56:00 +0200 | [diff] [blame] | 1387 | pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1388 | } |
| 1389 | } |
| 1390 | |
| 1391 | static void collect_system_info(struct raminfo *info) |
| 1392 | { |
| 1393 | u32 capid0[3]; |
| 1394 | int i; |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 1395 | unsigned int channel; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1396 | |
Angel Pons | b600d41 | 2021-01-16 16:33:48 +0100 | [diff] [blame] | 1397 | for (i = 0; i < 3; i++) { |
| 1398 | capid0[i] = pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2)); |
| 1399 | printk(BIOS_DEBUG, "CAPID0[%d] = 0x%08x\n", i, capid0[i]); |
| 1400 | } |
| 1401 | info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID); |
| 1402 | printk(BIOS_DEBUG, "Revision ID: 0x%x\n", info->revision); |
| 1403 | printk(BIOS_DEBUG, "Device ID: 0x%x\n", pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)); |
| 1404 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1405 | info->max_supported_clock_speed_index = (~capid0[1] & 7); |
| 1406 | |
| 1407 | if ((capid0[1] >> 11) & 1) |
| 1408 | info->uma_enabled = 0; |
| 1409 | else |
| 1410 | gav(info->uma_enabled = |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 1411 | pci_read_config8(NORTHBRIDGE, DEVEN) & 8); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1412 | /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */ |
| 1413 | info->silicon_revision = 0; |
| 1414 | |
| 1415 | if (capid0[2] & 2) { |
| 1416 | info->silicon_revision = 0; |
| 1417 | info->max_supported_clock_speed_index = 2; |
| 1418 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 1419 | if (info->populated_ranks[channel][0][0] |
| 1420 | && (info->spd[channel][0][MODULE_TYPE] & 0xf) == |
| 1421 | 3) { |
| 1422 | info->silicon_revision = 2; |
| 1423 | info->max_supported_clock_speed_index = 1; |
| 1424 | } |
| 1425 | } else { |
| 1426 | switch (((capid0[2] >> 18) & 1) + 2 * ((capid0[1] >> 3) & 1)) { |
| 1427 | case 1: |
| 1428 | case 2: |
| 1429 | info->silicon_revision = 3; |
| 1430 | break; |
| 1431 | case 3: |
| 1432 | info->silicon_revision = 0; |
| 1433 | break; |
| 1434 | case 0: |
| 1435 | info->silicon_revision = 2; |
| 1436 | break; |
| 1437 | } |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 1438 | switch (pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)) { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1439 | case 0x40: |
| 1440 | info->silicon_revision = 0; |
| 1441 | break; |
| 1442 | case 0x48: |
| 1443 | info->silicon_revision = 1; |
| 1444 | break; |
| 1445 | } |
| 1446 | } |
| 1447 | } |
| 1448 | |
| 1449 | static void write_training_data(struct raminfo *info) |
| 1450 | { |
| 1451 | int tm, channel, slot, rank, lane; |
| 1452 | if (info->revision < 8) |
| 1453 | return; |
| 1454 | |
| 1455 | for (tm = 0; tm < 4; tm++) |
| 1456 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 1457 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 1458 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 1459 | for (lane = 0; lane < 9; lane++) |
| 1460 | write_500(info, channel, |
| 1461 | info-> |
| 1462 | cached_training-> |
| 1463 | lane_timings[tm] |
| 1464 | [channel][slot][rank] |
| 1465 | [lane], |
| 1466 | get_timing_register_addr |
| 1467 | (lane, tm, slot, |
| 1468 | rank), 9, 0); |
| 1469 | write_1d0(info->cached_training->reg_178, 0x178, 7, 1); |
| 1470 | write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1); |
| 1471 | } |
| 1472 | |
| 1473 | static void dump_timings(struct raminfo *info) |
| 1474 | { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1475 | int channel, slot, rank, lane, i; |
Arthur Heymans | c892db6 | 2019-10-14 19:05:14 +0200 | [diff] [blame] | 1476 | printk(RAM_SPEW, "Timings:\n"); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1477 | FOR_POPULATED_RANKS { |
Arthur Heymans | c892db6 | 2019-10-14 19:05:14 +0200 | [diff] [blame] | 1478 | printk(RAM_SPEW, "channel %d, slot %d, rank %d\n", channel, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1479 | slot, rank); |
| 1480 | for (lane = 0; lane < 9; lane++) { |
Arthur Heymans | c892db6 | 2019-10-14 19:05:14 +0200 | [diff] [blame] | 1481 | printk(RAM_SPEW, "lane %d: ", lane); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1482 | for (i = 0; i < 4; i++) { |
Arthur Heymans | c892db6 | 2019-10-14 19:05:14 +0200 | [diff] [blame] | 1483 | printk(RAM_SPEW, "%x (%x) ", |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1484 | read_500(info, channel, |
| 1485 | get_timing_register_addr |
| 1486 | (lane, i, slot, rank), |
| 1487 | 9), |
| 1488 | info->training. |
| 1489 | lane_timings[i][channel][slot][rank] |
| 1490 | [lane]); |
| 1491 | } |
Arthur Heymans | c892db6 | 2019-10-14 19:05:14 +0200 | [diff] [blame] | 1492 | printk(RAM_SPEW, "\n"); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1493 | } |
| 1494 | } |
Arthur Heymans | c892db6 | 2019-10-14 19:05:14 +0200 | [diff] [blame] | 1495 | printk(RAM_SPEW, "[178] = %x (%x)\n", read_1d0(0x178, 7), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1496 | info->training.reg_178); |
Arthur Heymans | c892db6 | 2019-10-14 19:05:14 +0200 | [diff] [blame] | 1497 | printk(RAM_SPEW, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1498 | info->training.reg_10b); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1499 | } |
| 1500 | |
Vladimir Serbinenko | f7a42de | 2014-01-09 11:10:04 +0100 | [diff] [blame] | 1501 | /* Read timings and other registers that need to be restored verbatim and |
| 1502 | put them to CBMEM. |
| 1503 | */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1504 | static void save_timings(struct raminfo *info) |
| 1505 | { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1506 | struct ram_training train; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1507 | int channel, slot, rank, lane, i; |
| 1508 | |
| 1509 | train = info->training; |
| 1510 | FOR_POPULATED_RANKS for (lane = 0; lane < 9; lane++) |
| 1511 | for (i = 0; i < 4; i++) |
| 1512 | train.lane_timings[i][channel][slot][rank][lane] = |
| 1513 | read_500(info, channel, |
| 1514 | get_timing_register_addr(lane, i, slot, |
| 1515 | rank), 9); |
| 1516 | train.reg_178 = read_1d0(0x178, 7); |
| 1517 | train.reg_10b = read_1d0(0x10b, 6); |
| 1518 | |
Vladimir Serbinenko | f7a42de | 2014-01-09 11:10:04 +0100 | [diff] [blame] | 1519 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 1520 | u32 reg32; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1521 | reg32 = MCHBAR32((channel << 10) + 0x274); |
Vladimir Serbinenko | f7a42de | 2014-01-09 11:10:04 +0100 | [diff] [blame] | 1522 | train.reg274265[channel][0] = reg32 >> 16; |
| 1523 | train.reg274265[channel][1] = reg32 & 0xffff; |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 1524 | train.reg274265[channel][2] = |
| 1525 | MCHBAR16((channel << 10) + 0x265) >> 8; |
Vladimir Serbinenko | f7a42de | 2014-01-09 11:10:04 +0100 | [diff] [blame] | 1526 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1527 | train.reg2ca9_bit0 = MCHBAR8(0x2ca9) & 1; |
| 1528 | train.reg_6dc = MCHBAR32(0x6dc); |
| 1529 | train.reg_6e8 = MCHBAR32(0x6e8); |
Vladimir Serbinenko | f7a42de | 2014-01-09 11:10:04 +0100 | [diff] [blame] | 1530 | |
Arthur Heymans | b328209 | 2019-04-14 17:53:28 +0200 | [diff] [blame] | 1531 | printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc); |
| 1532 | printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8); |
Vladimir Serbinenko | f7a42de | 2014-01-09 11:10:04 +0100 | [diff] [blame] | 1533 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1534 | /* Save the MRC S3 restore data to cbmem */ |
Arthur Heymans | dc71e25 | 2018-01-29 10:14:48 +0100 | [diff] [blame] | 1535 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, |
| 1536 | &train, sizeof(train)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1537 | } |
| 1538 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1539 | static const struct ram_training *get_cached_training(void) |
| 1540 | { |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 1541 | return mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 1542 | MRC_CACHE_VERSION, |
| 1543 | NULL); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1544 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1545 | |
| 1546 | /* FIXME: add timeout. */ |
| 1547 | static void wait_heci_ready(void) |
| 1548 | { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1549 | while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c |
| 1550 | ; |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1551 | |
| 1552 | write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1553 | } |
| 1554 | |
| 1555 | /* FIXME: add timeout. */ |
| 1556 | static void wait_heci_cb_avail(int len) |
| 1557 | { |
| 1558 | union { |
| 1559 | struct mei_csr csr; |
| 1560 | u32 raw; |
| 1561 | } csr; |
| 1562 | |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 1563 | while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) |
| 1564 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1565 | |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1566 | do { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1567 | csr.raw = read32(DEFAULT_HECIBAR + 0x4); |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1568 | } while (len > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - |
| 1569 | csr.csr.buffer_read_ptr)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1570 | } |
| 1571 | |
Elyes HAOUAS | fd051dc | 2018-07-08 12:39:34 +0200 | [diff] [blame] | 1572 | static void send_heci_packet(struct mei_header *head, u32 *payload) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1573 | { |
| 1574 | int len = (head->length + 3) / 4; |
| 1575 | int i; |
| 1576 | |
| 1577 | wait_heci_cb_avail(len + 1); |
| 1578 | |
| 1579 | /* FIXME: handle leftovers correctly. */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1580 | write32(DEFAULT_HECIBAR + 0, *(u32 *) head); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1581 | for (i = 0; i < len - 1; i++) |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1582 | write32(DEFAULT_HECIBAR + 0, payload[i]); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1583 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1584 | write32(DEFAULT_HECIBAR + 0, payload[i] & ((1 << (8 * len)) - 1)); |
| 1585 | write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1586 | } |
| 1587 | |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1588 | static void send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1589 | { |
| 1590 | struct mei_header head; |
| 1591 | int maxlen; |
| 1592 | |
| 1593 | wait_heci_ready(); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1594 | maxlen = (read32(DEFAULT_HECIBAR + 0x4) >> 24) * 4 - 4; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1595 | |
| 1596 | while (len) { |
| 1597 | int cur = len; |
| 1598 | if (cur > maxlen) { |
| 1599 | cur = maxlen; |
| 1600 | head.is_complete = 0; |
| 1601 | } else |
| 1602 | head.is_complete = 1; |
| 1603 | head.length = cur; |
| 1604 | head.reserved = 0; |
| 1605 | head.client_address = clientaddress; |
| 1606 | head.host_address = hostaddress; |
| 1607 | send_heci_packet(&head, (u32 *) msg); |
| 1608 | len -= cur; |
| 1609 | msg += cur; |
| 1610 | } |
| 1611 | } |
| 1612 | |
| 1613 | /* FIXME: Add timeout. */ |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1614 | static int recv_heci_packet(struct mei_header *head, u32 *packet, u32 *packet_size) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1615 | { |
| 1616 | union { |
| 1617 | struct mei_csr csr; |
| 1618 | u32 raw; |
| 1619 | } csr; |
| 1620 | int i = 0; |
| 1621 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1622 | write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1623 | do { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1624 | csr.raw = read32(DEFAULT_HECIBAR + 0xc); |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1625 | } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); |
| 1626 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1627 | *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1628 | if (!head->length) { |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1629 | write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1630 | *packet_size = 0; |
| 1631 | return 0; |
| 1632 | } |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1633 | if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1634 | *packet_size = 0; |
| 1635 | return -1; |
| 1636 | } |
| 1637 | |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1638 | do { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1639 | csr.raw = read32(DEFAULT_HECIBAR + 0xc); |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1640 | } while (((head->length + 3) >> 2) > |
| 1641 | (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1642 | |
| 1643 | for (i = 0; i < (head->length + 3) >> 2; i++) |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1644 | packet[i++] = read32(DEFAULT_HECIBAR + 0x8); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1645 | *packet_size = head->length; |
| 1646 | if (!csr.csr.ready) |
| 1647 | *packet_size = 0; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1648 | write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1649 | return 0; |
| 1650 | } |
| 1651 | |
| 1652 | /* FIXME: Add timeout. */ |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1653 | static int recv_heci_message(u32 *message, u32 *message_size) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1654 | { |
| 1655 | struct mei_header head; |
| 1656 | int current_position; |
| 1657 | |
| 1658 | current_position = 0; |
| 1659 | while (1) { |
| 1660 | u32 current_size; |
| 1661 | current_size = *message_size - current_position; |
| 1662 | if (recv_heci_packet |
Angel Pons | 8690746 | 2020-09-14 18:48:59 +0200 | [diff] [blame] | 1663 | (&head, message + (current_position >> 2), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1664 | ¤t_size) == -1) |
| 1665 | break; |
| 1666 | if (!current_size) |
| 1667 | break; |
| 1668 | current_position += current_size; |
| 1669 | if (head.is_complete) { |
| 1670 | *message_size = current_position; |
| 1671 | return 0; |
| 1672 | } |
| 1673 | |
| 1674 | if (current_position >= *message_size) |
| 1675 | break; |
| 1676 | } |
| 1677 | *message_size = 0; |
| 1678 | return -1; |
| 1679 | } |
| 1680 | |
Angel Pons | 55f11e2 | 2020-09-14 19:06:53 +0200 | [diff] [blame] | 1681 | static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1682 | { |
Patrick Rudolph | a1ef213 | 2020-09-08 17:23:04 +0200 | [diff] [blame] | 1683 | volatile struct uma_reply { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1684 | u8 group_id; |
| 1685 | u8 command; |
| 1686 | u8 reserved; |
| 1687 | u8 result; |
| 1688 | u8 field2; |
| 1689 | u8 unk3[0x48 - 4 - 1]; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 1690 | } __packed reply; |
Elyes HAOUAS | e1d1fe4 | 2020-06-17 14:04:45 +0200 | [diff] [blame] | 1691 | |
| 1692 | /* FIXME: recv_heci_message() does not always initialize 'reply' */ |
| 1693 | reply.command = 0; |
| 1694 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1695 | struct uma_message { |
| 1696 | u8 group_id; |
| 1697 | u8 cmd; |
| 1698 | u8 reserved; |
| 1699 | u8 result; |
| 1700 | u32 c2; |
| 1701 | u64 heci_uma_addr; |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1702 | u32 heci_uma_size; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1703 | u16 c3; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 1704 | } __packed msg = { |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1705 | .group_id = 0, |
| 1706 | .cmd = MKHI_SET_UMA, |
| 1707 | .reserved = 0, |
| 1708 | .result = 0, |
| 1709 | .c2 = 0x82, |
| 1710 | .heci_uma_addr = heci_uma_addr, |
| 1711 | .heci_uma_size = heci_uma_size, |
| 1712 | .c3 = 0, |
| 1713 | }; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1714 | u32 reply_size; |
| 1715 | |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1716 | send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1717 | |
| 1718 | reply_size = sizeof(reply); |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1719 | if (recv_heci_message((u32 *) &reply, &reply_size) == -1) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1720 | return; |
| 1721 | |
| 1722 | if (reply.command != (MKHI_SET_UMA | (1 << 7))) |
| 1723 | die("HECI init failed\n"); |
| 1724 | } |
| 1725 | |
| 1726 | static void setup_heci_uma(struct raminfo *info) |
| 1727 | { |
Angel Pons | 4447996 | 2021-02-24 23:08:27 +0100 | [diff] [blame^] | 1728 | if (!info->memory_reserved_for_heci_mb || !(pci_read_config32(HECIDEV, 0x40) & 0x20)) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1729 | return; |
| 1730 | |
Angel Pons | 36592bf | 2020-09-14 18:52:44 +0200 | [diff] [blame] | 1731 | const u64 heci_uma_addr = |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1732 | ((u64) |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1733 | ((((u64)pci_read_config16(NORTHBRIDGE, TOM)) << 6) - |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1734 | info->memory_reserved_for_heci_mb)) << 20; |
| 1735 | |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 1736 | pci_read_config32(NORTHBRIDGE, DMIBAR); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1737 | if (info->memory_reserved_for_heci_mb) { |
Angel Pons | 3b264d0 | 2020-09-15 00:25:49 +0200 | [diff] [blame] | 1738 | DMIBAR32(DMIVC0RCTL) &= ~0x80; |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 1739 | RCBA32(0x14) &= ~0x80; |
Angel Pons | 3b264d0 | 2020-09-15 00:25:49 +0200 | [diff] [blame] | 1740 | DMIBAR32(DMIVC1RCTL) &= ~0x80; |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 1741 | RCBA32(0x20) &= ~0x80; |
Angel Pons | 3b264d0 | 2020-09-15 00:25:49 +0200 | [diff] [blame] | 1742 | DMIBAR32(DMIVCPRCTL) &= ~0x80; |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 1743 | RCBA32(0x30) &= ~0x80; |
Angel Pons | 3b264d0 | 2020-09-15 00:25:49 +0200 | [diff] [blame] | 1744 | DMIBAR32(DMIVCMRCTL) &= ~0x80; |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 1745 | RCBA32(0x40) &= ~0x80; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1746 | |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 1747 | RCBA32(0x40) = 0x87000080; // OK |
Angel Pons | 3b264d0 | 2020-09-15 00:25:49 +0200 | [diff] [blame] | 1748 | DMIBAR32(DMIVCMRCTL) = 0x87000080; // OK |
Angel Pons | eb53793 | 2020-09-14 19:18:11 +0200 | [diff] [blame] | 1749 | |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 1750 | while ((RCBA16(0x46) & 2) && DMIBAR16(DMIVCMRSTS) & VCMNP) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1751 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1752 | } |
| 1753 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 1754 | MCHBAR32(0x24) = 0x10000 + info->memory_reserved_for_heci_mb; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1755 | |
Angel Pons | 55f11e2 | 2020-09-14 19:06:53 +0200 | [diff] [blame] | 1756 | send_heci_uma_message(heci_uma_addr, info->memory_reserved_for_heci_mb); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1757 | |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 1758 | pci_write_config32(HECIDEV, 0x10, 0x0); |
| 1759 | pci_write_config8(HECIDEV, 0x4, 0x0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1760 | } |
| 1761 | |
| 1762 | static int have_match_ranks(struct raminfo *info, int channel, int ranks) |
| 1763 | { |
| 1764 | int ranks_in_channel; |
| 1765 | ranks_in_channel = info->populated_ranks[channel][0][0] |
| 1766 | + info->populated_ranks[channel][0][1] |
| 1767 | + info->populated_ranks[channel][1][0] |
| 1768 | + info->populated_ranks[channel][1][1]; |
| 1769 | |
| 1770 | /* empty channel */ |
| 1771 | if (ranks_in_channel == 0) |
| 1772 | return 1; |
| 1773 | |
| 1774 | if (ranks_in_channel != ranks) |
| 1775 | return 0; |
| 1776 | /* single slot */ |
| 1777 | if (info->populated_ranks[channel][0][0] != |
| 1778 | info->populated_ranks[channel][1][0]) |
| 1779 | return 1; |
| 1780 | if (info->populated_ranks[channel][0][1] != |
| 1781 | info->populated_ranks[channel][1][1]) |
| 1782 | return 1; |
| 1783 | if (info->is_x16_module[channel][0] != info->is_x16_module[channel][1]) |
| 1784 | return 0; |
| 1785 | if (info->density[channel][0] != info->density[channel][1]) |
| 1786 | return 0; |
| 1787 | return 1; |
| 1788 | } |
| 1789 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1790 | static void read_4090(struct raminfo *info) |
| 1791 | { |
| 1792 | int i, channel, slot, rank, lane; |
| 1793 | for (i = 0; i < 2; i++) |
| 1794 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 1795 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 1796 | for (lane = 0; lane < 9; lane++) |
| 1797 | info->training. |
| 1798 | lane_timings[0][i][slot][rank][lane] |
| 1799 | = 32; |
| 1800 | |
| 1801 | for (i = 1; i < 4; i++) |
| 1802 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 1803 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 1804 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 1805 | for (lane = 0; lane < 9; lane++) { |
| 1806 | info->training. |
| 1807 | lane_timings[i][channel] |
| 1808 | [slot][rank][lane] = |
| 1809 | read_500(info, channel, |
| 1810 | get_timing_register_addr |
| 1811 | (lane, i, slot, |
| 1812 | rank), 9) |
| 1813 | + (i == 1) * 11; // !!!! |
| 1814 | } |
| 1815 | |
| 1816 | } |
| 1817 | |
| 1818 | static u32 get_etalon2(int flip, u32 addr) |
| 1819 | { |
| 1820 | const u16 invmask[] = { |
| 1821 | 0xaaaa, 0x6db6, 0x4924, 0xeeee, 0xcccc, 0x8888, 0x7bde, 0x739c, |
| 1822 | 0x6318, 0x4210, 0xefbe, 0xcf3c, 0x8e38, 0x0c30, 0x0820 |
| 1823 | }; |
| 1824 | u32 ret; |
| 1825 | u32 comp4 = addr / 480; |
| 1826 | addr %= 480; |
| 1827 | u32 comp1 = addr & 0xf; |
| 1828 | u32 comp2 = (addr >> 4) & 1; |
| 1829 | u32 comp3 = addr >> 5; |
| 1830 | |
| 1831 | if (comp4) |
| 1832 | ret = 0x1010101 << (comp4 - 1); |
| 1833 | else |
| 1834 | ret = 0; |
| 1835 | if (flip ^ (((invmask[comp3] >> comp1) ^ comp2) & 1)) |
| 1836 | ret = ~ret; |
| 1837 | |
| 1838 | return ret; |
| 1839 | } |
| 1840 | |
Arthur Heymans | e7dd380 | 2019-11-25 12:09:33 +0100 | [diff] [blame] | 1841 | static void disable_cache_region(void) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1842 | { |
| 1843 | msr_t msr = {.lo = 0, .hi = 0 }; |
| 1844 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 1845 | wrmsr(MTRR_PHYS_BASE(3), msr); |
| 1846 | wrmsr(MTRR_PHYS_MASK(3), msr); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1847 | } |
| 1848 | |
Arthur Heymans | e7dd380 | 2019-11-25 12:09:33 +0100 | [diff] [blame] | 1849 | static void enable_cache_region(unsigned int base, unsigned int size) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1850 | { |
| 1851 | msr_t msr; |
| 1852 | msr.lo = base | MTRR_TYPE_WRPROT; |
| 1853 | msr.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 1854 | wrmsr(MTRR_PHYS_BASE(3), msr); |
| 1855 | msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRR_DEF_TYPE_EN) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1856 | & 0xffffffff); |
| 1857 | msr.hi = 0x0000000f; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 1858 | wrmsr(MTRR_PHYS_MASK(3), msr); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1859 | } |
| 1860 | |
| 1861 | static void flush_cache(u32 start, u32 size) |
| 1862 | { |
| 1863 | u32 end; |
| 1864 | u32 addr; |
| 1865 | |
| 1866 | end = start + (ALIGN_DOWN(size + 4096, 4096)); |
| 1867 | for (addr = start; addr < end; addr += 64) |
Patrick Rudolph | 819c206 | 2019-11-29 19:27:37 +0100 | [diff] [blame] | 1868 | clflush((void *)(uintptr_t)addr); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1869 | } |
| 1870 | |
| 1871 | static void clear_errors(void) |
| 1872 | { |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 1873 | pci_write_config8(NORTHBRIDGE, 0xc0, 0x01); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1874 | } |
| 1875 | |
| 1876 | static void write_testing(struct raminfo *info, int totalrank, int flip) |
| 1877 | { |
| 1878 | int nwrites = 0; |
| 1879 | /* in 8-byte units. */ |
| 1880 | u32 offset; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1881 | u8 *base; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1882 | |
Patrick Rudolph | 819c206 | 2019-11-29 19:27:37 +0100 | [diff] [blame] | 1883 | base = (u8 *)(uintptr_t)(totalrank << 28); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1884 | for (offset = 0; offset < 9 * 480; offset += 2) { |
| 1885 | write32(base + offset * 8, get_etalon2(flip, offset)); |
| 1886 | write32(base + offset * 8 + 4, get_etalon2(flip, offset)); |
| 1887 | write32(base + offset * 8 + 8, get_etalon2(flip, offset + 1)); |
| 1888 | write32(base + offset * 8 + 12, get_etalon2(flip, offset + 1)); |
| 1889 | nwrites += 4; |
| 1890 | if (nwrites >= 320) { |
| 1891 | clear_errors(); |
| 1892 | nwrites = 0; |
| 1893 | } |
| 1894 | } |
| 1895 | } |
| 1896 | |
| 1897 | static u8 check_testing(struct raminfo *info, u8 total_rank, int flip) |
| 1898 | { |
| 1899 | u8 failmask = 0; |
| 1900 | int i; |
| 1901 | int comp1, comp2, comp3; |
| 1902 | u32 failxor[2] = { 0, 0 }; |
| 1903 | |
Arthur Heymans | e7dd380 | 2019-11-25 12:09:33 +0100 | [diff] [blame] | 1904 | enable_cache_region((total_rank << 28), 1728 * 5 * 4); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1905 | |
| 1906 | for (comp3 = 0; comp3 < 9 && failmask != 0xff; comp3++) { |
| 1907 | for (comp1 = 0; comp1 < 4; comp1++) |
| 1908 | for (comp2 = 0; comp2 < 60; comp2++) { |
| 1909 | u32 re[4]; |
| 1910 | u32 curroffset = |
| 1911 | comp3 * 8 * 60 + 2 * comp1 + 8 * comp2; |
| 1912 | read128((total_rank << 28) | (curroffset << 3), |
| 1913 | (u64 *) re); |
| 1914 | failxor[0] |= |
| 1915 | get_etalon2(flip, curroffset) ^ re[0]; |
| 1916 | failxor[1] |= |
| 1917 | get_etalon2(flip, curroffset) ^ re[1]; |
| 1918 | failxor[0] |= |
| 1919 | get_etalon2(flip, curroffset | 1) ^ re[2]; |
| 1920 | failxor[1] |= |
| 1921 | get_etalon2(flip, curroffset | 1) ^ re[3]; |
| 1922 | } |
| 1923 | for (i = 0; i < 8; i++) |
| 1924 | if ((0xff << (8 * (i % 4))) & failxor[i / 4]) |
| 1925 | failmask |= 1 << i; |
| 1926 | } |
Arthur Heymans | e7dd380 | 2019-11-25 12:09:33 +0100 | [diff] [blame] | 1927 | disable_cache_region(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1928 | flush_cache((total_rank << 28), 1728 * 5 * 4); |
| 1929 | return failmask; |
| 1930 | } |
| 1931 | |
| 1932 | const u32 seed1[0x18] = { |
| 1933 | 0x3a9d5ab5, 0x576cb65b, 0x555773b6, 0x2ab772ee, |
| 1934 | 0x555556ee, 0x3a9d5ab5, 0x576cb65b, 0x555773b6, |
| 1935 | 0x2ab772ee, 0x555556ee, 0x5155a555, 0x5155a555, |
| 1936 | 0x5155a555, 0x5155a555, 0x3a9d5ab5, 0x576cb65b, |
| 1937 | 0x555773b6, 0x2ab772ee, 0x555556ee, 0x55d6b4a5, |
| 1938 | 0x366d6b3a, 0x2ae5ddbb, 0x3b9ddbb7, 0x55d6b4a5, |
| 1939 | }; |
| 1940 | |
| 1941 | static u32 get_seed2(int a, int b) |
| 1942 | { |
| 1943 | const u32 seed2[5] = { |
| 1944 | 0x55555555, 0x33333333, 0x2e555a55, 0x55555555, |
| 1945 | 0x5b6db6db, |
| 1946 | }; |
| 1947 | u32 r; |
| 1948 | r = seed2[(a + (a >= 10)) / 5]; |
| 1949 | return b ? ~r : r; |
| 1950 | } |
| 1951 | |
| 1952 | static int make_shift(int comp2, int comp5, int x) |
| 1953 | { |
| 1954 | const u8 seed3[32] = { |
| 1955 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 1956 | 0x00, 0x00, 0x38, 0x1c, 0x3c, 0x18, 0x38, 0x38, |
| 1957 | 0x38, 0x38, 0x38, 0x38, 0x0f, 0x0f, 0x0f, 0x0f, |
| 1958 | 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, |
| 1959 | }; |
| 1960 | |
| 1961 | return (comp2 - ((seed3[comp5] >> (x & 7)) & 1)) & 0x1f; |
| 1962 | } |
| 1963 | |
| 1964 | static u32 get_etalon(int flip, u32 addr) |
| 1965 | { |
| 1966 | u32 mask_byte = 0; |
| 1967 | int comp1 = (addr >> 1) & 1; |
| 1968 | int comp2 = (addr >> 3) & 0x1f; |
| 1969 | int comp3 = (addr >> 8) & 0xf; |
| 1970 | int comp4 = (addr >> 12) & 0xf; |
| 1971 | int comp5 = (addr >> 16) & 0x1f; |
| 1972 | u32 mask_bit = ~(0x10001 << comp3); |
| 1973 | u32 part1; |
| 1974 | u32 part2; |
| 1975 | int byte; |
| 1976 | |
| 1977 | part2 = |
| 1978 | ((seed1[comp5] >> |
| 1979 | make_shift(comp2, comp5, |
| 1980 | (comp3 >> 3) | (comp1 << 2) | 2)) & 1) ^ flip; |
| 1981 | part1 = |
| 1982 | ((seed1[comp5] >> |
| 1983 | make_shift(comp2, comp5, |
| 1984 | (comp3 >> 3) | (comp1 << 2) | 0)) & 1) ^ flip; |
| 1985 | |
| 1986 | for (byte = 0; byte < 4; byte++) |
| 1987 | if ((get_seed2(comp5, comp4) >> |
| 1988 | make_shift(comp2, comp5, (byte | (comp1 << 2)))) & 1) |
| 1989 | mask_byte |= 0xff << (8 * byte); |
| 1990 | |
| 1991 | return (mask_bit & mask_byte) | (part1 << comp3) | (part2 << |
| 1992 | (comp3 + 16)); |
| 1993 | } |
| 1994 | |
| 1995 | static void |
| 1996 | write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block, |
| 1997 | char flip) |
| 1998 | { |
| 1999 | int i; |
| 2000 | for (i = 0; i < 2048; i++) |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 2001 | write32p((totalrank << 28) | (region << 25) | (block << 16) | |
| 2002 | (i << 2), get_etalon(flip, (block << 16) | (i << 2))); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2003 | } |
| 2004 | |
| 2005 | static u8 |
| 2006 | check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block, |
| 2007 | char flip) |
| 2008 | { |
| 2009 | u8 failmask = 0; |
| 2010 | u32 failxor[2]; |
| 2011 | int i; |
| 2012 | int comp1, comp2, comp3; |
| 2013 | |
| 2014 | failxor[0] = 0; |
| 2015 | failxor[1] = 0; |
| 2016 | |
Arthur Heymans | e7dd380 | 2019-11-25 12:09:33 +0100 | [diff] [blame] | 2017 | enable_cache_region(totalrank << 28, 134217728); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2018 | for (comp3 = 0; comp3 < 2 && failmask != 0xff; comp3++) { |
| 2019 | for (comp1 = 0; comp1 < 16; comp1++) |
| 2020 | for (comp2 = 0; comp2 < 64; comp2++) { |
| 2021 | u32 addr = |
| 2022 | (totalrank << 28) | (region << 25) | (block |
| 2023 | << 16) |
| 2024 | | (comp3 << 12) | (comp2 << 6) | (comp1 << |
| 2025 | 2); |
| 2026 | failxor[comp1 & 1] |= |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 2027 | read32p(addr) ^ get_etalon(flip, addr); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2028 | } |
| 2029 | for (i = 0; i < 8; i++) |
| 2030 | if ((0xff << (8 * (i % 4))) & failxor[i / 4]) |
| 2031 | failmask |= 1 << i; |
| 2032 | } |
Arthur Heymans | e7dd380 | 2019-11-25 12:09:33 +0100 | [diff] [blame] | 2033 | disable_cache_region(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2034 | flush_cache((totalrank << 28) | (region << 25) | (block << 16), 16384); |
| 2035 | return failmask; |
| 2036 | } |
| 2037 | |
| 2038 | static int check_bounded(unsigned short *vals, u16 bound) |
| 2039 | { |
| 2040 | int i; |
| 2041 | |
| 2042 | for (i = 0; i < 8; i++) |
| 2043 | if (vals[i] < bound) |
| 2044 | return 0; |
| 2045 | return 1; |
| 2046 | } |
| 2047 | |
| 2048 | enum state { |
| 2049 | BEFORE_USABLE = 0, AT_USABLE = 1, AT_MARGIN = 2, COMPLETE = 3 |
| 2050 | }; |
| 2051 | |
| 2052 | static int validate_state(enum state *in) |
| 2053 | { |
| 2054 | int i; |
| 2055 | for (i = 0; i < 8; i++) |
| 2056 | if (in[i] != COMPLETE) |
| 2057 | return 0; |
| 2058 | return 1; |
| 2059 | } |
| 2060 | |
| 2061 | static void |
Elyes HAOUAS | fd051dc | 2018-07-08 12:39:34 +0200 | [diff] [blame] | 2062 | do_fsm(enum state *state, u16 *counter, |
| 2063 | u8 fail_mask, int margin, int uplimit, |
| 2064 | u8 *res_low, u8 *res_high, u8 val) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2065 | { |
| 2066 | int lane; |
| 2067 | |
| 2068 | for (lane = 0; lane < 8; lane++) { |
| 2069 | int is_fail = (fail_mask >> lane) & 1; |
| 2070 | switch (state[lane]) { |
| 2071 | case BEFORE_USABLE: |
| 2072 | if (!is_fail) { |
| 2073 | counter[lane] = 1; |
| 2074 | state[lane] = AT_USABLE; |
| 2075 | break; |
| 2076 | } |
| 2077 | counter[lane] = 0; |
| 2078 | state[lane] = BEFORE_USABLE; |
| 2079 | break; |
| 2080 | case AT_USABLE: |
| 2081 | if (!is_fail) { |
| 2082 | ++counter[lane]; |
| 2083 | if (counter[lane] >= margin) { |
| 2084 | state[lane] = AT_MARGIN; |
| 2085 | res_low[lane] = val - margin + 1; |
| 2086 | break; |
| 2087 | } |
| 2088 | state[lane] = 1; |
| 2089 | break; |
| 2090 | } |
| 2091 | counter[lane] = 0; |
| 2092 | state[lane] = BEFORE_USABLE; |
| 2093 | break; |
| 2094 | case AT_MARGIN: |
| 2095 | if (is_fail) { |
| 2096 | state[lane] = COMPLETE; |
| 2097 | res_high[lane] = val - 1; |
| 2098 | } else { |
| 2099 | counter[lane]++; |
| 2100 | state[lane] = AT_MARGIN; |
| 2101 | if (val == uplimit) { |
| 2102 | state[lane] = COMPLETE; |
| 2103 | res_high[lane] = uplimit; |
| 2104 | } |
| 2105 | } |
| 2106 | break; |
| 2107 | case COMPLETE: |
| 2108 | break; |
| 2109 | } |
| 2110 | } |
| 2111 | } |
| 2112 | |
| 2113 | static void |
| 2114 | train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, |
| 2115 | u8 total_rank, u8 reg_178, int first_run, int niter, |
| 2116 | timing_bounds_t * timings) |
| 2117 | { |
| 2118 | int lane; |
| 2119 | enum state state[8]; |
| 2120 | u16 count[8]; |
| 2121 | u8 lower_usable[8]; |
| 2122 | u8 upper_usable[8]; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2123 | unsigned short num_successfully_checked[8]; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2124 | u8 reg1b3; |
Elyes HAOUAS | 019a253 | 2019-05-25 11:13:43 +0200 | [diff] [blame] | 2125 | int i; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2126 | |
Elyes HAOUAS | 019a253 | 2019-05-25 11:13:43 +0200 | [diff] [blame] | 2127 | for (i = 0; i < 8; i++) |
| 2128 | state[i] = BEFORE_USABLE; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2129 | |
| 2130 | if (!first_run) { |
| 2131 | int is_all_ok = 1; |
| 2132 | for (lane = 0; lane < 8; lane++) |
| 2133 | if (timings[reg_178][channel][slot][rank][lane]. |
| 2134 | smallest == |
| 2135 | timings[reg_178][channel][slot][rank][lane]. |
| 2136 | largest) { |
| 2137 | timings[reg_178][channel][slot][rank][lane]. |
| 2138 | smallest = 0; |
| 2139 | timings[reg_178][channel][slot][rank][lane]. |
| 2140 | largest = 0; |
| 2141 | is_all_ok = 0; |
| 2142 | } |
| 2143 | if (is_all_ok) { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2144 | for (i = 0; i < 8; i++) |
| 2145 | state[i] = COMPLETE; |
| 2146 | } |
| 2147 | } |
| 2148 | |
| 2149 | for (reg1b3 = 0; reg1b3 < 0x30 && !validate_state(state); reg1b3++) { |
| 2150 | u8 failmask = 0; |
| 2151 | write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1); |
| 2152 | write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1); |
| 2153 | failmask = check_testing(info, total_rank, 0); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2154 | MCHBAR32_OR(0xfb0, 0x00030000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2155 | do_fsm(state, count, failmask, 5, 47, lower_usable, |
| 2156 | upper_usable, reg1b3); |
| 2157 | } |
| 2158 | |
| 2159 | if (reg1b3) { |
| 2160 | write_1d0(0, 0x1b3, 6, 1); |
| 2161 | write_1d0(0, 0x1a3, 6, 1); |
| 2162 | for (lane = 0; lane < 8; lane++) { |
| 2163 | if (state[lane] == COMPLETE) { |
| 2164 | timings[reg_178][channel][slot][rank][lane]. |
| 2165 | smallest = |
| 2166 | lower_usable[lane] + |
| 2167 | (info->training. |
| 2168 | lane_timings[0][channel][slot][rank][lane] |
| 2169 | & 0x3F) - 32; |
| 2170 | timings[reg_178][channel][slot][rank][lane]. |
| 2171 | largest = |
| 2172 | upper_usable[lane] + |
| 2173 | (info->training. |
| 2174 | lane_timings[0][channel][slot][rank][lane] |
| 2175 | & 0x3F) - 32; |
| 2176 | } |
| 2177 | } |
| 2178 | } |
| 2179 | |
| 2180 | if (!first_run) { |
| 2181 | for (lane = 0; lane < 8; lane++) |
| 2182 | if (state[lane] == COMPLETE) { |
| 2183 | write_500(info, channel, |
| 2184 | timings[reg_178][channel][slot][rank] |
| 2185 | [lane].smallest, |
| 2186 | get_timing_register_addr(lane, 0, |
| 2187 | slot, rank), |
| 2188 | 9, 1); |
| 2189 | write_500(info, channel, |
| 2190 | timings[reg_178][channel][slot][rank] |
| 2191 | [lane].smallest + |
| 2192 | info->training. |
| 2193 | lane_timings[1][channel][slot][rank] |
| 2194 | [lane] |
| 2195 | - |
| 2196 | info->training. |
| 2197 | lane_timings[0][channel][slot][rank] |
| 2198 | [lane], get_timing_register_addr(lane, |
| 2199 | 1, |
| 2200 | slot, |
| 2201 | rank), |
| 2202 | 9, 1); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2203 | num_successfully_checked[lane] = 0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2204 | } else |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2205 | num_successfully_checked[lane] = -1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2206 | |
| 2207 | do { |
| 2208 | u8 failmask = 0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2209 | for (i = 0; i < niter; i++) { |
| 2210 | if (failmask == 0xFF) |
| 2211 | break; |
| 2212 | failmask |= |
| 2213 | check_testing_type2(info, total_rank, 2, i, |
| 2214 | 0); |
| 2215 | failmask |= |
| 2216 | check_testing_type2(info, total_rank, 3, i, |
| 2217 | 1); |
| 2218 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2219 | MCHBAR32_OR(0xfb0, 0x00030000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2220 | for (lane = 0; lane < 8; lane++) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2221 | if (num_successfully_checked[lane] != 0xffff) { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2222 | if ((1 << lane) & failmask) { |
| 2223 | if (timings[reg_178][channel] |
| 2224 | [slot][rank][lane]. |
| 2225 | largest <= |
| 2226 | timings[reg_178][channel] |
| 2227 | [slot][rank][lane].smallest) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2228 | num_successfully_checked |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2229 | [lane] = -1; |
| 2230 | else { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2231 | num_successfully_checked |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2232 | [lane] = 0; |
| 2233 | timings[reg_178] |
| 2234 | [channel][slot] |
| 2235 | [rank][lane]. |
| 2236 | smallest++; |
| 2237 | write_500(info, channel, |
| 2238 | timings |
| 2239 | [reg_178] |
| 2240 | [channel] |
| 2241 | [slot][rank] |
| 2242 | [lane]. |
| 2243 | smallest, |
| 2244 | get_timing_register_addr |
| 2245 | (lane, 0, |
| 2246 | slot, rank), |
| 2247 | 9, 1); |
| 2248 | write_500(info, channel, |
| 2249 | timings |
| 2250 | [reg_178] |
| 2251 | [channel] |
| 2252 | [slot][rank] |
| 2253 | [lane]. |
| 2254 | smallest + |
| 2255 | info-> |
| 2256 | training. |
| 2257 | lane_timings |
| 2258 | [1][channel] |
| 2259 | [slot][rank] |
| 2260 | [lane] |
| 2261 | - |
| 2262 | info-> |
| 2263 | training. |
| 2264 | lane_timings |
| 2265 | [0][channel] |
| 2266 | [slot][rank] |
| 2267 | [lane], |
| 2268 | get_timing_register_addr |
| 2269 | (lane, 1, |
| 2270 | slot, rank), |
| 2271 | 9, 1); |
| 2272 | } |
| 2273 | } else |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2274 | num_successfully_checked[lane] |
| 2275 | ++; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2276 | } |
| 2277 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2278 | while (!check_bounded(num_successfully_checked, 2)) |
| 2279 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2280 | |
| 2281 | for (lane = 0; lane < 8; lane++) |
| 2282 | if (state[lane] == COMPLETE) { |
| 2283 | write_500(info, channel, |
| 2284 | timings[reg_178][channel][slot][rank] |
| 2285 | [lane].largest, |
| 2286 | get_timing_register_addr(lane, 0, |
| 2287 | slot, rank), |
| 2288 | 9, 1); |
| 2289 | write_500(info, channel, |
| 2290 | timings[reg_178][channel][slot][rank] |
| 2291 | [lane].largest + |
| 2292 | info->training. |
| 2293 | lane_timings[1][channel][slot][rank] |
| 2294 | [lane] |
| 2295 | - |
| 2296 | info->training. |
| 2297 | lane_timings[0][channel][slot][rank] |
| 2298 | [lane], get_timing_register_addr(lane, |
| 2299 | 1, |
| 2300 | slot, |
| 2301 | rank), |
| 2302 | 9, 1); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2303 | num_successfully_checked[lane] = 0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2304 | } else |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2305 | num_successfully_checked[lane] = -1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2306 | |
| 2307 | do { |
| 2308 | int failmask = 0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2309 | for (i = 0; i < niter; i++) { |
| 2310 | if (failmask == 0xFF) |
| 2311 | break; |
| 2312 | failmask |= |
| 2313 | check_testing_type2(info, total_rank, 2, i, |
| 2314 | 0); |
| 2315 | failmask |= |
| 2316 | check_testing_type2(info, total_rank, 3, i, |
| 2317 | 1); |
| 2318 | } |
| 2319 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2320 | MCHBAR32_OR(0xfb0, 0x00030000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2321 | for (lane = 0; lane < 8; lane++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2322 | if (num_successfully_checked[lane] != 0xffff) { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2323 | if ((1 << lane) & failmask) { |
| 2324 | if (timings[reg_178][channel] |
| 2325 | [slot][rank][lane]. |
| 2326 | largest <= |
| 2327 | timings[reg_178][channel] |
| 2328 | [slot][rank][lane]. |
| 2329 | smallest) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2330 | num_successfully_checked |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2331 | [lane] = -1; |
| 2332 | } else { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2333 | num_successfully_checked |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2334 | [lane] = 0; |
| 2335 | timings[reg_178] |
| 2336 | [channel][slot] |
| 2337 | [rank][lane]. |
| 2338 | largest--; |
| 2339 | write_500(info, channel, |
| 2340 | timings |
| 2341 | [reg_178] |
| 2342 | [channel] |
| 2343 | [slot][rank] |
| 2344 | [lane]. |
| 2345 | largest, |
| 2346 | get_timing_register_addr |
| 2347 | (lane, 0, |
| 2348 | slot, rank), |
| 2349 | 9, 1); |
| 2350 | write_500(info, channel, |
| 2351 | timings |
| 2352 | [reg_178] |
| 2353 | [channel] |
| 2354 | [slot][rank] |
| 2355 | [lane]. |
| 2356 | largest + |
| 2357 | info-> |
| 2358 | training. |
| 2359 | lane_timings |
| 2360 | [1][channel] |
| 2361 | [slot][rank] |
| 2362 | [lane] |
| 2363 | - |
| 2364 | info-> |
| 2365 | training. |
| 2366 | lane_timings |
| 2367 | [0][channel] |
| 2368 | [slot][rank] |
| 2369 | [lane], |
| 2370 | get_timing_register_addr |
| 2371 | (lane, 1, |
| 2372 | slot, rank), |
| 2373 | 9, 1); |
| 2374 | } |
| 2375 | } else |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2376 | num_successfully_checked[lane] |
| 2377 | ++; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2378 | } |
| 2379 | } |
| 2380 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2381 | while (!check_bounded(num_successfully_checked, 3)) |
| 2382 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2383 | |
| 2384 | for (lane = 0; lane < 8; lane++) { |
| 2385 | write_500(info, channel, |
| 2386 | info->training. |
| 2387 | lane_timings[0][channel][slot][rank][lane], |
| 2388 | get_timing_register_addr(lane, 0, slot, rank), |
| 2389 | 9, 1); |
| 2390 | write_500(info, channel, |
| 2391 | info->training. |
| 2392 | lane_timings[1][channel][slot][rank][lane], |
| 2393 | get_timing_register_addr(lane, 1, slot, rank), |
| 2394 | 9, 1); |
| 2395 | if (timings[reg_178][channel][slot][rank][lane]. |
| 2396 | largest <= |
| 2397 | timings[reg_178][channel][slot][rank][lane]. |
| 2398 | smallest) { |
| 2399 | timings[reg_178][channel][slot][rank][lane]. |
| 2400 | largest = 0; |
| 2401 | timings[reg_178][channel][slot][rank][lane]. |
| 2402 | smallest = 0; |
| 2403 | } |
| 2404 | } |
| 2405 | } |
| 2406 | } |
| 2407 | |
| 2408 | static void set_10b(struct raminfo *info, u8 val) |
| 2409 | { |
| 2410 | int channel; |
| 2411 | int slot, rank; |
| 2412 | int lane; |
| 2413 | |
| 2414 | if (read_1d0(0x10b, 6) == val) |
| 2415 | return; |
| 2416 | |
| 2417 | write_1d0(val, 0x10b, 6, 1); |
| 2418 | |
| 2419 | FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 9; lane++) { |
| 2420 | u16 reg_500; |
| 2421 | reg_500 = read_500(info, channel, |
| 2422 | get_timing_register_addr(lane, 0, slot, |
| 2423 | rank), 9); |
| 2424 | if (val == 1) { |
| 2425 | if (lut16[info->clock_speed_index] <= reg_500) |
| 2426 | reg_500 -= lut16[info->clock_speed_index]; |
| 2427 | else |
| 2428 | reg_500 = 0; |
| 2429 | } else { |
| 2430 | reg_500 += lut16[info->clock_speed_index]; |
| 2431 | } |
| 2432 | write_500(info, channel, reg_500, |
| 2433 | get_timing_register_addr(lane, 0, slot, rank), 9, 1); |
| 2434 | } |
| 2435 | } |
| 2436 | |
| 2437 | static void set_ecc(int onoff) |
| 2438 | { |
| 2439 | int channel; |
| 2440 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 2441 | u8 t; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2442 | t = MCHBAR8((channel << 10) + 0x5f8); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2443 | if (onoff) |
| 2444 | t |= 1; |
| 2445 | else |
| 2446 | t &= ~1; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2447 | MCHBAR8((channel << 10) + 0x5f8) = t; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2448 | } |
| 2449 | } |
| 2450 | |
| 2451 | static void set_178(u8 val) |
| 2452 | { |
| 2453 | if (val >= 31) |
| 2454 | val = val - 31; |
| 2455 | else |
| 2456 | val = 63 - val; |
| 2457 | |
| 2458 | write_1d0(2 * val, 0x178, 7, 1); |
| 2459 | } |
| 2460 | |
| 2461 | static void |
| 2462 | write_500_timings_type(struct raminfo *info, int channel, int slot, int rank, |
| 2463 | int type) |
| 2464 | { |
| 2465 | int lane; |
| 2466 | |
| 2467 | for (lane = 0; lane < 8; lane++) |
| 2468 | write_500(info, channel, |
| 2469 | info->training. |
| 2470 | lane_timings[type][channel][slot][rank][lane], |
| 2471 | get_timing_register_addr(lane, type, slot, rank), 9, |
| 2472 | 0); |
| 2473 | } |
| 2474 | |
| 2475 | static void |
| 2476 | try_timing_offsets(struct raminfo *info, int channel, |
| 2477 | int slot, int rank, int totalrank) |
| 2478 | { |
| 2479 | u16 count[8]; |
| 2480 | enum state state[8]; |
| 2481 | u8 lower_usable[8], upper_usable[8]; |
| 2482 | int lane; |
| 2483 | int i; |
| 2484 | int flip = 1; |
| 2485 | int timing_offset; |
| 2486 | |
| 2487 | for (i = 0; i < 8; i++) |
| 2488 | state[i] = BEFORE_USABLE; |
| 2489 | |
| 2490 | memset(count, 0, sizeof(count)); |
| 2491 | |
| 2492 | for (lane = 0; lane < 8; lane++) |
| 2493 | write_500(info, channel, |
| 2494 | info->training. |
| 2495 | lane_timings[2][channel][slot][rank][lane] + 32, |
| 2496 | get_timing_register_addr(lane, 3, slot, rank), 9, 1); |
| 2497 | |
| 2498 | for (timing_offset = 0; !validate_state(state) && timing_offset < 64; |
| 2499 | timing_offset++) { |
| 2500 | u8 failmask; |
| 2501 | write_1d0(timing_offset ^ 32, 0x1bb, 6, 1); |
| 2502 | failmask = 0; |
| 2503 | for (i = 0; i < 2 && failmask != 0xff; i++) { |
| 2504 | flip = !flip; |
| 2505 | write_testing(info, totalrank, flip); |
| 2506 | failmask |= check_testing(info, totalrank, flip); |
| 2507 | } |
| 2508 | do_fsm(state, count, failmask, 10, 63, lower_usable, |
| 2509 | upper_usable, timing_offset); |
| 2510 | } |
| 2511 | write_1d0(0, 0x1bb, 6, 1); |
| 2512 | dump_timings(info); |
| 2513 | if (!validate_state(state)) |
| 2514 | die("Couldn't discover DRAM timings (1)\n"); |
| 2515 | |
| 2516 | for (lane = 0; lane < 8; lane++) { |
| 2517 | u8 bias = 0; |
| 2518 | |
| 2519 | if (info->silicon_revision) { |
| 2520 | int usable_length; |
| 2521 | |
| 2522 | usable_length = upper_usable[lane] - lower_usable[lane]; |
| 2523 | if (usable_length >= 20) { |
| 2524 | bias = usable_length / 2 - 10; |
| 2525 | if (bias >= 2) |
| 2526 | bias = 2; |
| 2527 | } |
| 2528 | } |
| 2529 | write_500(info, channel, |
| 2530 | info->training. |
| 2531 | lane_timings[2][channel][slot][rank][lane] + |
| 2532 | (upper_usable[lane] + lower_usable[lane]) / 2 - bias, |
| 2533 | get_timing_register_addr(lane, 3, slot, rank), 9, 1); |
| 2534 | info->training.timing2_bounds[channel][slot][rank][lane][0] = |
| 2535 | info->training.lane_timings[2][channel][slot][rank][lane] + |
| 2536 | lower_usable[lane]; |
| 2537 | info->training.timing2_bounds[channel][slot][rank][lane][1] = |
| 2538 | info->training.lane_timings[2][channel][slot][rank][lane] + |
| 2539 | upper_usable[lane]; |
| 2540 | info->training.timing2_offset[channel][slot][rank][lane] = |
| 2541 | info->training.lane_timings[2][channel][slot][rank][lane]; |
| 2542 | } |
| 2543 | } |
| 2544 | |
| 2545 | static u8 |
| 2546 | choose_training(struct raminfo *info, int channel, int slot, int rank, |
| 2547 | int lane, timing_bounds_t * timings, u8 center_178) |
| 2548 | { |
| 2549 | u16 central_weight; |
| 2550 | u16 side_weight; |
| 2551 | unsigned int sum = 0, count = 0; |
| 2552 | u8 span; |
| 2553 | u8 lower_margin, upper_margin; |
| 2554 | u8 reg_178; |
| 2555 | u8 result; |
| 2556 | |
| 2557 | span = 12; |
| 2558 | central_weight = 20; |
| 2559 | side_weight = 20; |
| 2560 | if (info->silicon_revision == 1 && channel == 1) { |
| 2561 | central_weight = 5; |
| 2562 | side_weight = 20; |
| 2563 | if ((info-> |
| 2564 | populated_ranks_mask[1] ^ (info-> |
| 2565 | populated_ranks_mask[1] >> 2)) & |
| 2566 | 1) |
| 2567 | span = 18; |
| 2568 | } |
| 2569 | if ((info->populated_ranks_mask[0] & 5) == 5) { |
| 2570 | central_weight = 20; |
| 2571 | side_weight = 20; |
| 2572 | } |
| 2573 | if (info->clock_speed_index >= 2 |
| 2574 | && (info->populated_ranks_mask[0] & 5) == 5 && slot == 1) { |
| 2575 | if (info->silicon_revision == 1) { |
| 2576 | switch (channel) { |
| 2577 | case 0: |
| 2578 | if (lane == 1) { |
| 2579 | central_weight = 10; |
| 2580 | side_weight = 20; |
| 2581 | } |
| 2582 | break; |
| 2583 | case 1: |
| 2584 | if (lane == 6) { |
| 2585 | side_weight = 5; |
| 2586 | central_weight = 20; |
| 2587 | } |
| 2588 | break; |
| 2589 | } |
| 2590 | } |
| 2591 | if (info->silicon_revision == 0 && channel == 0 && lane == 0) { |
| 2592 | side_weight = 5; |
| 2593 | central_weight = 20; |
| 2594 | } |
| 2595 | } |
| 2596 | for (reg_178 = center_178 - span; reg_178 <= center_178 + span; |
| 2597 | reg_178 += span) { |
| 2598 | u8 smallest; |
| 2599 | u8 largest; |
| 2600 | largest = timings[reg_178][channel][slot][rank][lane].largest; |
| 2601 | smallest = timings[reg_178][channel][slot][rank][lane].smallest; |
| 2602 | if (largest - smallest + 1 >= 5) { |
| 2603 | unsigned int weight; |
| 2604 | if (reg_178 == center_178) |
| 2605 | weight = central_weight; |
| 2606 | else |
| 2607 | weight = side_weight; |
| 2608 | sum += weight * (largest + smallest); |
| 2609 | count += weight; |
| 2610 | } |
| 2611 | } |
| 2612 | dump_timings(info); |
| 2613 | if (count == 0) |
| 2614 | die("Couldn't discover DRAM timings (2)\n"); |
| 2615 | result = sum / (2 * count); |
| 2616 | lower_margin = |
| 2617 | result - timings[center_178][channel][slot][rank][lane].smallest; |
| 2618 | upper_margin = |
| 2619 | timings[center_178][channel][slot][rank][lane].largest - result; |
| 2620 | if (upper_margin < 10 && lower_margin > 10) |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 2621 | result -= MIN(lower_margin - 10, 10 - upper_margin); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2622 | if (upper_margin > 10 && lower_margin < 10) |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 2623 | result += MIN(upper_margin - 10, 10 - lower_margin); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2624 | return result; |
| 2625 | } |
| 2626 | |
| 2627 | #define STANDARD_MIN_MARGIN 5 |
| 2628 | |
| 2629 | static u8 choose_reg178(struct raminfo *info, timing_bounds_t * timings) |
| 2630 | { |
| 2631 | u16 margin[64]; |
| 2632 | int lane, rank, slot, channel; |
| 2633 | u8 reg178; |
| 2634 | int count = 0, sum = 0; |
| 2635 | |
| 2636 | for (reg178 = reg178_min[info->clock_speed_index]; |
| 2637 | reg178 < reg178_max[info->clock_speed_index]; |
| 2638 | reg178 += reg178_step[info->clock_speed_index]) { |
| 2639 | margin[reg178] = -1; |
| 2640 | FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { |
| 2641 | int curmargin = |
| 2642 | timings[reg178][channel][slot][rank][lane].largest - |
| 2643 | timings[reg178][channel][slot][rank][lane]. |
| 2644 | smallest + 1; |
| 2645 | if (curmargin < margin[reg178]) |
| 2646 | margin[reg178] = curmargin; |
| 2647 | } |
| 2648 | if (margin[reg178] >= STANDARD_MIN_MARGIN) { |
| 2649 | u16 weight; |
| 2650 | weight = margin[reg178] - STANDARD_MIN_MARGIN; |
| 2651 | sum += weight * reg178; |
| 2652 | count += weight; |
| 2653 | } |
| 2654 | } |
| 2655 | dump_timings(info); |
| 2656 | if (count == 0) |
| 2657 | die("Couldn't discover DRAM timings (3)\n"); |
| 2658 | |
| 2659 | u8 threshold; |
| 2660 | |
| 2661 | for (threshold = 30; threshold >= 5; threshold--) { |
| 2662 | int usable_length = 0; |
| 2663 | int smallest_fount = 0; |
| 2664 | for (reg178 = reg178_min[info->clock_speed_index]; |
| 2665 | reg178 < reg178_max[info->clock_speed_index]; |
| 2666 | reg178 += reg178_step[info->clock_speed_index]) |
| 2667 | if (margin[reg178] >= threshold) { |
| 2668 | usable_length += |
| 2669 | reg178_step[info->clock_speed_index]; |
| 2670 | info->training.reg178_largest = |
| 2671 | reg178 - |
| 2672 | 2 * reg178_step[info->clock_speed_index]; |
| 2673 | |
| 2674 | if (!smallest_fount) { |
| 2675 | smallest_fount = 1; |
| 2676 | info->training.reg178_smallest = |
| 2677 | reg178 + |
| 2678 | reg178_step[info-> |
| 2679 | clock_speed_index]; |
| 2680 | } |
| 2681 | } |
| 2682 | if (usable_length >= 0x21) |
| 2683 | break; |
| 2684 | } |
| 2685 | |
| 2686 | return sum / count; |
| 2687 | } |
| 2688 | |
| 2689 | static int check_cached_sanity(struct raminfo *info) |
| 2690 | { |
| 2691 | int lane; |
| 2692 | int slot, rank; |
| 2693 | int channel; |
| 2694 | |
| 2695 | if (!info->cached_training) |
| 2696 | return 0; |
| 2697 | |
| 2698 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 2699 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 2700 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 2701 | for (lane = 0; lane < 8 + info->use_ecc; lane++) { |
| 2702 | u16 cached_value, estimation_value; |
| 2703 | cached_value = |
| 2704 | info->cached_training-> |
| 2705 | lane_timings[1][channel][slot][rank] |
| 2706 | [lane]; |
| 2707 | if (cached_value >= 0x18 |
| 2708 | && cached_value <= 0x1E7) { |
| 2709 | estimation_value = |
| 2710 | info->training. |
| 2711 | lane_timings[1][channel] |
| 2712 | [slot][rank][lane]; |
| 2713 | if (estimation_value < |
| 2714 | cached_value - 24) |
| 2715 | return 0; |
| 2716 | if (estimation_value > |
| 2717 | cached_value + 24) |
| 2718 | return 0; |
| 2719 | } |
| 2720 | } |
| 2721 | return 1; |
| 2722 | } |
| 2723 | |
| 2724 | static int try_cached_training(struct raminfo *info) |
| 2725 | { |
| 2726 | u8 saved_243[2]; |
| 2727 | u8 tm; |
| 2728 | |
| 2729 | int channel, slot, rank, lane; |
| 2730 | int flip = 1; |
| 2731 | int i, j; |
| 2732 | |
| 2733 | if (!check_cached_sanity(info)) |
| 2734 | return 0; |
| 2735 | |
| 2736 | info->training.reg178_center = info->cached_training->reg178_center; |
| 2737 | info->training.reg178_smallest = info->cached_training->reg178_smallest; |
| 2738 | info->training.reg178_largest = info->cached_training->reg178_largest; |
| 2739 | memcpy(&info->training.timing_bounds, |
| 2740 | &info->cached_training->timing_bounds, |
| 2741 | sizeof(info->training.timing_bounds)); |
| 2742 | memcpy(&info->training.timing_offset, |
| 2743 | &info->cached_training->timing_offset, |
| 2744 | sizeof(info->training.timing_offset)); |
| 2745 | |
| 2746 | write_1d0(2, 0x142, 3, 1); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2747 | saved_243[0] = MCHBAR8(0x243); |
| 2748 | saved_243[1] = MCHBAR8(0x643); |
| 2749 | MCHBAR8(0x243) = saved_243[0] | 2; |
| 2750 | MCHBAR8(0x643) = saved_243[1] | 2; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2751 | set_ecc(0); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 2752 | pci_write_config16(NORTHBRIDGE, 0xc8, 3); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2753 | if (read_1d0(0x10b, 6) & 1) |
| 2754 | set_10b(info, 0); |
| 2755 | for (tm = 0; tm < 2; tm++) { |
| 2756 | int totalrank; |
| 2757 | |
| 2758 | set_178(tm ? info->cached_training->reg178_largest : info-> |
| 2759 | cached_training->reg178_smallest); |
| 2760 | |
| 2761 | totalrank = 0; |
| 2762 | /* Check timing ranges. With i == 0 we check smallest one and with |
| 2763 | i == 1 the largest bound. With j == 0 we check that on the bound |
| 2764 | it still works whereas with j == 1 we check that just outside of |
| 2765 | bound we fail. |
| 2766 | */ |
| 2767 | FOR_POPULATED_RANKS_BACKWARDS { |
| 2768 | for (i = 0; i < 2; i++) { |
| 2769 | for (lane = 0; lane < 8; lane++) { |
| 2770 | write_500(info, channel, |
| 2771 | info->cached_training-> |
| 2772 | timing2_bounds[channel][slot] |
| 2773 | [rank][lane][i], |
| 2774 | get_timing_register_addr(lane, |
| 2775 | 3, |
| 2776 | slot, |
| 2777 | rank), |
| 2778 | 9, 1); |
| 2779 | |
| 2780 | if (!i) |
| 2781 | write_500(info, channel, |
| 2782 | info-> |
| 2783 | cached_training-> |
| 2784 | timing2_offset |
| 2785 | [channel][slot][rank] |
| 2786 | [lane], |
| 2787 | get_timing_register_addr |
| 2788 | (lane, 2, slot, rank), |
| 2789 | 9, 1); |
| 2790 | write_500(info, channel, |
| 2791 | i ? info->cached_training-> |
| 2792 | timing_bounds[tm][channel] |
| 2793 | [slot][rank][lane]. |
| 2794 | largest : info-> |
| 2795 | cached_training-> |
| 2796 | timing_bounds[tm][channel] |
| 2797 | [slot][rank][lane].smallest, |
| 2798 | get_timing_register_addr(lane, |
| 2799 | 0, |
| 2800 | slot, |
| 2801 | rank), |
| 2802 | 9, 1); |
| 2803 | write_500(info, channel, |
| 2804 | info->cached_training-> |
| 2805 | timing_offset[channel][slot] |
| 2806 | [rank][lane] + |
| 2807 | (i ? info->cached_training-> |
| 2808 | timing_bounds[tm][channel] |
| 2809 | [slot][rank][lane]. |
| 2810 | largest : info-> |
| 2811 | cached_training-> |
| 2812 | timing_bounds[tm][channel] |
| 2813 | [slot][rank][lane]. |
| 2814 | smallest) - 64, |
| 2815 | get_timing_register_addr(lane, |
| 2816 | 1, |
| 2817 | slot, |
| 2818 | rank), |
| 2819 | 9, 1); |
| 2820 | } |
| 2821 | for (j = 0; j < 2; j++) { |
| 2822 | u8 failmask; |
| 2823 | u8 expected_failmask; |
| 2824 | char reg1b3; |
| 2825 | |
| 2826 | reg1b3 = (j == 1) + 4; |
| 2827 | reg1b3 = |
| 2828 | j == i ? reg1b3 : (-reg1b3) & 0x3f; |
| 2829 | write_1d0(reg1b3, 0x1bb, 6, 1); |
| 2830 | write_1d0(reg1b3, 0x1b3, 6, 1); |
| 2831 | write_1d0(reg1b3, 0x1a3, 6, 1); |
| 2832 | |
| 2833 | flip = !flip; |
| 2834 | write_testing(info, totalrank, flip); |
| 2835 | failmask = |
| 2836 | check_testing(info, totalrank, |
| 2837 | flip); |
| 2838 | expected_failmask = |
| 2839 | j == 0 ? 0x00 : 0xff; |
| 2840 | if (failmask != expected_failmask) |
| 2841 | goto fail; |
| 2842 | } |
| 2843 | } |
| 2844 | totalrank++; |
| 2845 | } |
| 2846 | } |
| 2847 | |
| 2848 | set_178(info->cached_training->reg178_center); |
| 2849 | if (info->use_ecc) |
| 2850 | set_ecc(1); |
| 2851 | write_training_data(info); |
| 2852 | write_1d0(0, 322, 3, 1); |
| 2853 | info->training = *info->cached_training; |
| 2854 | |
| 2855 | write_1d0(0, 0x1bb, 6, 1); |
| 2856 | write_1d0(0, 0x1b3, 6, 1); |
| 2857 | write_1d0(0, 0x1a3, 6, 1); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2858 | MCHBAR8(0x243) = saved_243[0]; |
| 2859 | MCHBAR8(0x643) = saved_243[1]; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2860 | |
| 2861 | return 1; |
| 2862 | |
| 2863 | fail: |
| 2864 | FOR_POPULATED_RANKS { |
| 2865 | write_500_timings_type(info, channel, slot, rank, 1); |
| 2866 | write_500_timings_type(info, channel, slot, rank, 2); |
| 2867 | write_500_timings_type(info, channel, slot, rank, 3); |
| 2868 | } |
| 2869 | |
| 2870 | write_1d0(0, 0x1bb, 6, 1); |
| 2871 | write_1d0(0, 0x1b3, 6, 1); |
| 2872 | write_1d0(0, 0x1a3, 6, 1); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2873 | MCHBAR8(0x243) = saved_243[0]; |
| 2874 | MCHBAR8(0x643) = saved_243[1]; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2875 | |
| 2876 | return 0; |
| 2877 | } |
| 2878 | |
| 2879 | static void do_ram_training(struct raminfo *info) |
| 2880 | { |
| 2881 | u8 saved_243[2]; |
| 2882 | int totalrank = 0; |
| 2883 | u8 reg_178; |
| 2884 | int niter; |
| 2885 | |
Matthias Gazzari | dfa5125 | 2018-05-19 00:44:20 +0200 | [diff] [blame] | 2886 | timing_bounds_t *timings = timings_car; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2887 | int lane, rank, slot, channel; |
| 2888 | u8 reg178_center; |
| 2889 | |
| 2890 | write_1d0(2, 0x142, 3, 1); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 2891 | saved_243[0] = MCHBAR8(0x243); |
| 2892 | saved_243[1] = MCHBAR8(0x643); |
| 2893 | MCHBAR8(0x243) = saved_243[0] | 2; |
| 2894 | MCHBAR8(0x643) = saved_243[1] | 2; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2895 | switch (info->clock_speed_index) { |
| 2896 | case 0: |
| 2897 | niter = 5; |
| 2898 | break; |
| 2899 | case 1: |
| 2900 | niter = 10; |
| 2901 | break; |
| 2902 | default: |
| 2903 | niter = 19; |
| 2904 | break; |
| 2905 | } |
| 2906 | set_ecc(0); |
| 2907 | |
| 2908 | FOR_POPULATED_RANKS_BACKWARDS { |
| 2909 | int i; |
| 2910 | |
| 2911 | write_500_timings_type(info, channel, slot, rank, 0); |
| 2912 | |
| 2913 | write_testing(info, totalrank, 0); |
| 2914 | for (i = 0; i < niter; i++) { |
| 2915 | write_testing_type2(info, totalrank, 2, i, 0); |
| 2916 | write_testing_type2(info, totalrank, 3, i, 1); |
| 2917 | } |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 2918 | pci_write_config8(NORTHBRIDGE, 0xc0, 0x01); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2919 | totalrank++; |
| 2920 | } |
| 2921 | |
| 2922 | if (reg178_min[info->clock_speed_index] < |
| 2923 | reg178_max[info->clock_speed_index]) |
| 2924 | memset(timings[reg178_min[info->clock_speed_index]], 0, |
| 2925 | sizeof(timings[0]) * |
| 2926 | (reg178_max[info->clock_speed_index] - |
| 2927 | reg178_min[info->clock_speed_index])); |
| 2928 | for (reg_178 = reg178_min[info->clock_speed_index]; |
| 2929 | reg_178 < reg178_max[info->clock_speed_index]; |
| 2930 | reg_178 += reg178_step[info->clock_speed_index]) { |
| 2931 | totalrank = 0; |
| 2932 | set_178(reg_178); |
| 2933 | for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) |
| 2934 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 2935 | for (rank = 0; rank < NUM_RANKS; rank++) { |
| 2936 | memset(&timings[reg_178][channel][slot] |
| 2937 | [rank][0].smallest, 0, 16); |
| 2938 | if (info-> |
| 2939 | populated_ranks[channel][slot] |
| 2940 | [rank]) { |
| 2941 | train_ram_at_178(info, channel, |
| 2942 | slot, rank, |
| 2943 | totalrank, |
| 2944 | reg_178, 1, |
| 2945 | niter, |
| 2946 | timings); |
| 2947 | totalrank++; |
| 2948 | } |
| 2949 | } |
| 2950 | } |
| 2951 | |
| 2952 | reg178_center = choose_reg178(info, timings); |
| 2953 | |
| 2954 | FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { |
| 2955 | info->training.timing_bounds[0][channel][slot][rank][lane]. |
| 2956 | smallest = |
| 2957 | timings[info->training. |
| 2958 | reg178_smallest][channel][slot][rank][lane]. |
| 2959 | smallest; |
| 2960 | info->training.timing_bounds[0][channel][slot][rank][lane]. |
| 2961 | largest = |
| 2962 | timings[info->training. |
| 2963 | reg178_smallest][channel][slot][rank][lane].largest; |
| 2964 | info->training.timing_bounds[1][channel][slot][rank][lane]. |
| 2965 | smallest = |
| 2966 | timings[info->training. |
| 2967 | reg178_largest][channel][slot][rank][lane].smallest; |
| 2968 | info->training.timing_bounds[1][channel][slot][rank][lane]. |
| 2969 | largest = |
| 2970 | timings[info->training. |
| 2971 | reg178_largest][channel][slot][rank][lane].largest; |
| 2972 | info->training.timing_offset[channel][slot][rank][lane] = |
| 2973 | info->training.lane_timings[1][channel][slot][rank][lane] |
| 2974 | - |
| 2975 | info->training.lane_timings[0][channel][slot][rank][lane] + |
| 2976 | 64; |
| 2977 | } |
| 2978 | |
| 2979 | if (info->silicon_revision == 1 |
| 2980 | && (info-> |
| 2981 | populated_ranks_mask[1] ^ (info-> |
| 2982 | populated_ranks_mask[1] >> 2)) & 1) { |
| 2983 | int ranks_after_channel1; |
| 2984 | |
| 2985 | totalrank = 0; |
| 2986 | for (reg_178 = reg178_center - 18; |
| 2987 | reg_178 <= reg178_center + 18; reg_178 += 18) { |
| 2988 | totalrank = 0; |
| 2989 | set_178(reg_178); |
| 2990 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 2991 | for (rank = 0; rank < NUM_RANKS; rank++) { |
| 2992 | if (info-> |
| 2993 | populated_ranks[1][slot][rank]) { |
| 2994 | train_ram_at_178(info, 1, slot, |
| 2995 | rank, |
| 2996 | totalrank, |
| 2997 | reg_178, 0, |
| 2998 | niter, |
| 2999 | timings); |
| 3000 | totalrank++; |
| 3001 | } |
| 3002 | } |
| 3003 | } |
| 3004 | ranks_after_channel1 = totalrank; |
| 3005 | |
| 3006 | for (reg_178 = reg178_center - 12; |
| 3007 | reg_178 <= reg178_center + 12; reg_178 += 12) { |
| 3008 | totalrank = ranks_after_channel1; |
| 3009 | set_178(reg_178); |
| 3010 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 3011 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 3012 | if (info-> |
| 3013 | populated_ranks[0][slot][rank]) { |
| 3014 | train_ram_at_178(info, 0, slot, |
| 3015 | rank, |
| 3016 | totalrank, |
| 3017 | reg_178, 0, |
| 3018 | niter, |
| 3019 | timings); |
| 3020 | totalrank++; |
| 3021 | } |
| 3022 | |
| 3023 | } |
| 3024 | } else { |
| 3025 | for (reg_178 = reg178_center - 12; |
| 3026 | reg_178 <= reg178_center + 12; reg_178 += 12) { |
| 3027 | totalrank = 0; |
| 3028 | set_178(reg_178); |
| 3029 | FOR_POPULATED_RANKS_BACKWARDS { |
| 3030 | train_ram_at_178(info, channel, slot, rank, |
| 3031 | totalrank, reg_178, 0, niter, |
| 3032 | timings); |
| 3033 | totalrank++; |
| 3034 | } |
| 3035 | } |
| 3036 | } |
| 3037 | |
| 3038 | set_178(reg178_center); |
| 3039 | FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { |
| 3040 | u16 tm0; |
| 3041 | |
| 3042 | tm0 = |
| 3043 | choose_training(info, channel, slot, rank, lane, timings, |
| 3044 | reg178_center); |
| 3045 | write_500(info, channel, tm0, |
| 3046 | get_timing_register_addr(lane, 0, slot, rank), 9, 1); |
| 3047 | write_500(info, channel, |
| 3048 | tm0 + |
| 3049 | info->training. |
| 3050 | lane_timings[1][channel][slot][rank][lane] - |
| 3051 | info->training. |
| 3052 | lane_timings[0][channel][slot][rank][lane], |
| 3053 | get_timing_register_addr(lane, 1, slot, rank), 9, 1); |
| 3054 | } |
| 3055 | |
| 3056 | totalrank = 0; |
| 3057 | FOR_POPULATED_RANKS_BACKWARDS { |
| 3058 | try_timing_offsets(info, channel, slot, rank, totalrank); |
| 3059 | totalrank++; |
| 3060 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3061 | MCHBAR8(0x243) = saved_243[0]; |
| 3062 | MCHBAR8(0x643) = saved_243[1]; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3063 | write_1d0(0, 0x142, 3, 1); |
| 3064 | info->training.reg178_center = reg178_center; |
| 3065 | } |
| 3066 | |
| 3067 | static void ram_training(struct raminfo *info) |
| 3068 | { |
| 3069 | u16 saved_fc4; |
| 3070 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3071 | saved_fc4 = MCHBAR16(0xfc4); |
| 3072 | MCHBAR16(0xfc4) = 0xffff; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3073 | |
| 3074 | if (info->revision >= 8) |
| 3075 | read_4090(info); |
| 3076 | |
| 3077 | if (!try_cached_training(info)) |
| 3078 | do_ram_training(info); |
| 3079 | if ((info->silicon_revision == 2 || info->silicon_revision == 3) |
| 3080 | && info->clock_speed_index < 2) |
| 3081 | set_10b(info, 1); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3082 | MCHBAR16(0xfc4) = saved_fc4; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3083 | } |
| 3084 | |
Angel Pons | 7a87c92 | 2021-01-15 22:50:41 +0100 | [diff] [blame] | 3085 | u16 get_max_timing(struct raminfo *info, int channel) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3086 | { |
| 3087 | int slot, rank, lane; |
| 3088 | u16 ret = 0; |
| 3089 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3090 | if ((MCHBAR8(0x2ca8) >> 2) < 1) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3091 | return 384; |
| 3092 | |
| 3093 | if (info->revision < 8) |
| 3094 | return 256; |
| 3095 | |
| 3096 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 3097 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 3098 | if (info->populated_ranks[channel][slot][rank]) |
| 3099 | for (lane = 0; lane < 8 + info->use_ecc; lane++) |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 3100 | ret = MAX(ret, read_500(info, channel, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3101 | get_timing_register_addr |
| 3102 | (lane, 0, slot, |
| 3103 | rank), 9)); |
| 3104 | return ret; |
| 3105 | } |
| 3106 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3107 | static void dmi_setup(void) |
| 3108 | { |
Angel Pons | d071c4d | 2020-09-14 23:51:35 +0200 | [diff] [blame] | 3109 | gav(DMIBAR8(0x254)); |
| 3110 | DMIBAR8(0x254) = 0x1; |
| 3111 | DMIBAR16(0x1b8) = 0x18f2; |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3112 | MCHBAR16_AND_OR(0x48, 0, 0x2); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3113 | |
Angel Pons | d071c4d | 2020-09-14 23:51:35 +0200 | [diff] [blame] | 3114 | DMIBAR32(0xd68) |= 0x08000000; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3115 | |
| 3116 | outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000, |
| 3117 | DEFAULT_GPIOBASE | 0x38); |
| 3118 | gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e |
| 3119 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3120 | |
Vladimir Serbinenko | 9817a37 | 2014-02-19 22:07:12 +0100 | [diff] [blame] | 3121 | void chipset_init(const int s3resume) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3122 | { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3123 | u8 x2ca8; |
Vladimir Serbinenko | 55391c4 | 2014-08-03 14:51:00 +0200 | [diff] [blame] | 3124 | u16 ggc; |
| 3125 | u8 gfxsize; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3126 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3127 | x2ca8 = MCHBAR8(0x2ca8); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3128 | if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { |
| 3129 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3130 | MCHBAR8(0x2ca8) = 0; |
Elyes HAOUAS | d45f338 | 2019-04-28 18:04:35 +0200 | [diff] [blame] | 3131 | system_reset(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3132 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3133 | |
| 3134 | dmi_setup(); |
| 3135 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3136 | MCHBAR16(0x1170) = 0xa880; |
| 3137 | MCHBAR8(0x11c1) = 0x1; |
| 3138 | MCHBAR16(0x1170) = 0xb880; |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3139 | MCHBAR8_AND_OR(0x1210, 0, 0x84); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3140 | |
Vladimir Serbinenko | 55391c4 | 2014-08-03 14:51:00 +0200 | [diff] [blame] | 3141 | if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { |
| 3142 | /* 0 for 32MB */ |
| 3143 | gfxsize = 0; |
| 3144 | } |
| 3145 | |
| 3146 | ggc = 0xb00 | ((gfxsize + 5) << 4); |
| 3147 | |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 3148 | pci_write_config16(NORTHBRIDGE, GGC, ggc | 2); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3149 | |
| 3150 | u16 deven; |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 3151 | deven = pci_read_config16(NORTHBRIDGE, DEVEN); // = 0x3 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3152 | |
| 3153 | if (deven & 8) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3154 | MCHBAR8(0x2c30) = 0x20; |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3155 | pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18 |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3156 | MCHBAR16_OR(0x2c30, 0x200); |
| 3157 | MCHBAR16(0x2c32) = 0x434; |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3158 | MCHBAR32_AND_OR(0x2c44, 0, 0x1053687); |
Angel Pons | aaea66a | 2020-09-15 00:41:14 +0200 | [diff] [blame] | 3159 | pci_read_config8(GMA, MSAC); // = 0x2 |
| 3160 | pci_write_config8(GMA, MSAC, 0x2); |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 3161 | RCBA8(0x2318); |
| 3162 | RCBA8(0x2318) = 0x47; |
| 3163 | RCBA8(0x2320); |
| 3164 | RCBA8(0x2320) = 0xfc; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3165 | } |
| 3166 | |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3167 | MCHBAR32_AND_OR(0x30, 0, 0x40); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3168 | |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 3169 | pci_write_config16(NORTHBRIDGE, GGC, ggc); |
Angel Pons | ee7fb34 | 2021-01-28 14:11:55 +0100 | [diff] [blame] | 3170 | gav(RCBA32(0x3428)); |
| 3171 | RCBA32(0x3428) = 0x1d; |
Vladimir Serbinenko | 9817a37 | 2014-02-19 22:07:12 +0100 | [diff] [blame] | 3172 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3173 | |
Angel Pons | 2668191 | 2021-01-15 21:36:28 +0100 | [diff] [blame] | 3174 | static u8 get_bits_420(const u32 reg32) |
| 3175 | { |
| 3176 | u8 val = 0; |
| 3177 | val |= (reg32 >> 4) & (1 << 0); |
| 3178 | val |= (reg32 >> 2) & (1 << 1); |
| 3179 | val |= (reg32 >> 0) & (1 << 2); |
| 3180 | return val; |
| 3181 | } |
| 3182 | |
Vladimir Serbinenko | 9817a37 | 2014-02-19 22:07:12 +0100 | [diff] [blame] | 3183 | void raminit(const int s3resume, const u8 *spd_addrmap) |
| 3184 | { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 3185 | unsigned int channel, slot, lane, rank; |
Vladimir Serbinenko | 9817a37 | 2014-02-19 22:07:12 +0100 | [diff] [blame] | 3186 | struct raminfo info; |
| 3187 | u8 x2ca8; |
Vladimir Serbinenko | b16f092 | 2014-06-07 16:27:27 +0200 | [diff] [blame] | 3188 | int cbmem_wasnot_inited; |
Vladimir Serbinenko | 9817a37 | 2014-02-19 22:07:12 +0100 | [diff] [blame] | 3189 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3190 | x2ca8 = MCHBAR8(0x2ca8); |
Arthur Heymans | b572c9d | 2019-10-14 18:18:46 +0200 | [diff] [blame] | 3191 | |
| 3192 | printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); |
| 3193 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3194 | memset(&info, 0x5a, sizeof(info)); |
| 3195 | |
| 3196 | info.last_500_command[0] = 0; |
| 3197 | info.last_500_command[1] = 0; |
| 3198 | |
| 3199 | info.fsb_frequency = 135 * 2; |
| 3200 | info.board_lane_delay[0] = 0x14; |
| 3201 | info.board_lane_delay[1] = 0x07; |
| 3202 | info.board_lane_delay[2] = 0x07; |
| 3203 | info.board_lane_delay[3] = 0x08; |
| 3204 | info.board_lane_delay[4] = 0x56; |
| 3205 | info.board_lane_delay[5] = 0x04; |
| 3206 | info.board_lane_delay[6] = 0x04; |
| 3207 | info.board_lane_delay[7] = 0x05; |
| 3208 | info.board_lane_delay[8] = 0x10; |
| 3209 | |
| 3210 | info.training.reg_178 = 0; |
| 3211 | info.training.reg_10b = 0; |
| 3212 | |
Angel Pons | a386829 | 2021-01-15 22:10:13 +0100 | [diff] [blame] | 3213 | /* Wait for some bit, maybe TXT clear. */ |
| 3214 | while (!(read8((u8 *)0xfed40000) & (1 << 7))) |
| 3215 | ; |
| 3216 | |
| 3217 | /* Wait for ME to be ready */ |
Angel Pons | 4447996 | 2021-02-24 23:08:27 +0100 | [diff] [blame^] | 3218 | if (intel_early_me_init() == 0) |
| 3219 | info.memory_reserved_for_heci_mb = intel_early_me_uma_size(); |
| 3220 | else |
| 3221 | info.memory_reserved_for_heci_mb = 0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3222 | |
| 3223 | /* before SPD */ |
| 3224 | timestamp_add_now(101); |
| 3225 | |
Felix Held | 29a9c07 | 2018-07-29 01:34:45 +0200 | [diff] [blame] | 3226 | if (!s3resume || 1) { // possible error |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3227 | memset(&info.populated_ranks, 0, sizeof(info.populated_ranks)); |
| 3228 | |
| 3229 | info.use_ecc = 1; |
| 3230 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Vladimir Serbinenko | 2ab8ec7 | 2014-02-20 14:34:56 +0100 | [diff] [blame] | 3231 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3232 | int v; |
| 3233 | int try; |
| 3234 | int addr; |
| 3235 | const u8 useful_addresses[] = { |
| 3236 | DEVICE_TYPE, |
| 3237 | MODULE_TYPE, |
| 3238 | DENSITY, |
| 3239 | RANKS_AND_DQ, |
| 3240 | MEMORY_BUS_WIDTH, |
| 3241 | TIMEBASE_DIVIDEND, |
| 3242 | TIMEBASE_DIVISOR, |
| 3243 | CYCLETIME, |
| 3244 | CAS_LATENCIES_LSB, |
| 3245 | CAS_LATENCIES_MSB, |
| 3246 | CAS_LATENCY_TIME, |
| 3247 | 0x11, 0x12, 0x13, 0x14, 0x15, |
| 3248 | 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, |
| 3249 | 0x1c, 0x1d, |
| 3250 | THERMAL_AND_REFRESH, |
| 3251 | 0x20, |
| 3252 | REFERENCE_RAW_CARD_USED, |
| 3253 | RANK1_ADDRESS_MAPPING, |
| 3254 | 0x75, 0x76, 0x77, 0x78, |
| 3255 | 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, |
| 3256 | 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, |
| 3257 | 0x85, 0x86, 0x87, 0x88, |
| 3258 | 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, |
| 3259 | 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, |
| 3260 | 0x95 |
| 3261 | }; |
Vladimir Serbinenko | 902626c | 2014-02-16 17:22:26 +0100 | [diff] [blame] | 3262 | if (!spd_addrmap[2 * channel + slot]) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3263 | continue; |
| 3264 | for (try = 0; try < 5; try++) { |
Vladimir Serbinenko | 902626c | 2014-02-16 17:22:26 +0100 | [diff] [blame] | 3265 | v = smbus_read_byte(spd_addrmap[2 * channel + slot], |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3266 | DEVICE_TYPE); |
| 3267 | if (v >= 0) |
| 3268 | break; |
| 3269 | } |
| 3270 | if (v < 0) |
| 3271 | continue; |
| 3272 | for (addr = 0; |
| 3273 | addr < |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 3274 | ARRAY_SIZE(useful_addresses); addr++) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3275 | gav(info. |
| 3276 | spd[channel][0][useful_addresses |
| 3277 | [addr]] = |
Vladimir Serbinenko | 902626c | 2014-02-16 17:22:26 +0100 | [diff] [blame] | 3278 | smbus_read_byte(spd_addrmap[2 * channel + slot], |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3279 | useful_addresses |
| 3280 | [addr])); |
| 3281 | if (info.spd[channel][0][DEVICE_TYPE] != 11) |
| 3282 | die("Only DDR3 is supported"); |
| 3283 | |
| 3284 | v = info.spd[channel][0][RANKS_AND_DQ]; |
| 3285 | info.populated_ranks[channel][0][0] = 1; |
| 3286 | info.populated_ranks[channel][0][1] = |
| 3287 | ((v >> 3) & 7); |
| 3288 | if (((v >> 3) & 7) > 1) |
| 3289 | die("At most 2 ranks are supported"); |
| 3290 | if ((v & 7) == 0 || (v & 7) > 2) |
| 3291 | die("Only x8 and x16 modules are supported"); |
| 3292 | if ((info. |
| 3293 | spd[channel][slot][MODULE_TYPE] & 0xF) != 2 |
| 3294 | && (info. |
| 3295 | spd[channel][slot][MODULE_TYPE] & 0xF) |
| 3296 | != 3) |
| 3297 | die("Registered memory is not supported"); |
| 3298 | info.is_x16_module[channel][0] = (v & 7) - 1; |
| 3299 | info.density[channel][slot] = |
| 3300 | info.spd[channel][slot][DENSITY] & 0xF; |
| 3301 | if (! |
| 3302 | (info. |
| 3303 | spd[channel][slot][MEMORY_BUS_WIDTH] & |
| 3304 | 0x18)) |
| 3305 | info.use_ecc = 0; |
| 3306 | } |
| 3307 | |
| 3308 | gav(0x55); |
| 3309 | |
| 3310 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 3311 | int v = 0; |
| 3312 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 3313 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 3314 | v |= info. |
| 3315 | populated_ranks[channel][slot][rank] |
| 3316 | << (2 * slot + rank); |
| 3317 | info.populated_ranks_mask[channel] = v; |
| 3318 | } |
| 3319 | |
| 3320 | gav(0x55); |
| 3321 | |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 3322 | gav(pci_read_config32(NORTHBRIDGE, CAPID0 + 4)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3323 | } |
| 3324 | |
| 3325 | /* after SPD */ |
| 3326 | timestamp_add_now(102); |
| 3327 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3328 | MCHBAR8_AND(0x2ca8, 0xfc); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3329 | |
| 3330 | collect_system_info(&info); |
| 3331 | calculate_timings(&info); |
| 3332 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3333 | if (!s3resume) { |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3334 | u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3335 | if (x2ca8 == 0 && (reg8 & 0x80)) { |
| 3336 | /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. |
| 3337 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 3338 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08); |
| 3339 | */ |
| 3340 | |
| 3341 | /* Clear bit7. */ |
| 3342 | |
| 3343 | pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, |
| 3344 | (reg8 & ~(1 << 7))); |
| 3345 | |
| 3346 | printk(BIOS_INFO, |
| 3347 | "Interrupted RAM init, reset required.\n"); |
Elyes HAOUAS | d45f338 | 2019-04-28 18:04:35 +0200 | [diff] [blame] | 3348 | system_reset(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3349 | } |
| 3350 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3351 | |
| 3352 | if (!s3resume && x2ca8 == 0) |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3353 | pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, |
| 3354 | pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3355 | |
| 3356 | compute_derived_timings(&info); |
| 3357 | |
Angel Pons | 56823f5 | 2021-01-16 11:27:33 +0100 | [diff] [blame] | 3358 | early_quickpath_init(&info, x2ca8); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3359 | |
Vladimir Serbinenko | f7a42de | 2014-01-09 11:10:04 +0100 | [diff] [blame] | 3360 | info.cached_training = get_cached_training(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3361 | |
Angel Pons | 7a87c92 | 2021-01-15 22:50:41 +0100 | [diff] [blame] | 3362 | if (x2ca8 == 0) |
| 3363 | late_quickpath_init(&info, s3resume); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3364 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3365 | MCHBAR32_OR(0x2c80, (1 << 24)); |
| 3366 | MCHBAR32(0x1804) = MCHBAR32(0x1c04) & ~(1 << 27); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3367 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3368 | MCHBAR8(0x2ca8); // !!!! |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3369 | |
| 3370 | if (x2ca8 == 0) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3371 | MCHBAR8_AND(0x2ca8, ~3); |
| 3372 | MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? |
Arthur Heymans | b572c9d | 2019-10-14 18:18:46 +0200 | [diff] [blame] | 3373 | /* This issues a CPU reset without resetting the platform */ |
| 3374 | printk(BIOS_DEBUG, "Issuing a CPU reset\n"); |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 3375 | /* Write back the S3 state to PM1_CNT to let the reset CPU |
| 3376 | know it also needs to take the s3 path. */ |
| 3377 | if (s3resume) |
| 3378 | write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) |
| 3379 | | (SLP_TYP_S3 << 10)); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3380 | MCHBAR32_OR(0x1af0, 0x10); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 3381 | halt(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3382 | } |
Angel Pons | 7a87c92 | 2021-01-15 22:50:41 +0100 | [diff] [blame] | 3383 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3384 | MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); // !!!! |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3385 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3386 | MCHBAR32_AND(0x2c80, ~(1 << 24)); |
| 3387 | |
Angel Pons | 9addda3 | 2020-07-22 18:37:32 +0200 | [diff] [blame] | 3388 | pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3389 | |
| 3390 | { |
| 3391 | u8 x2c20 = (MCHBAR16(0x2c20) >> 8) & 3; |
| 3392 | u16 x2c10 = MCHBAR16(0x2c10); |
| 3393 | u16 value = MCHBAR16(0x2c00); |
| 3394 | if (x2c20 == 0 && (x2c10 & 0x300) == 0) |
| 3395 | value |= (1 << 7); |
| 3396 | else |
| 3397 | value &= ~(1 << 0); |
| 3398 | |
| 3399 | MCHBAR16(0x2c00) = value; |
| 3400 | } |
| 3401 | |
| 3402 | udelay(1000); // !!!! |
| 3403 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3404 | write_1d0(0, 0x33d, 0, 0); |
| 3405 | write_500(&info, 0, 0, 0xb61, 0, 0); |
| 3406 | write_500(&info, 1, 0, 0xb61, 0, 0); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3407 | MCHBAR32(0x1a30) = 0x0; |
| 3408 | MCHBAR32(0x1a34) = 0x0; |
| 3409 | MCHBAR16(0x614) = 0xb5b | (info.populated_ranks[1][0][0] * 0x404) | |
| 3410 | (info.populated_ranks[0][0][0] * 0xa0); |
| 3411 | MCHBAR16(0x616) = 0x26a; |
| 3412 | MCHBAR32(0x134) = 0x856000; |
| 3413 | MCHBAR32(0x160) = 0x5ffffff; |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3414 | MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!! |
| 3415 | MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!! |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3416 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3417 | MCHBAR32(0x260 + (channel << 10)) = 0x30809ff | |
| 3418 | ((info.populated_ranks_mask[channel] & 3) << 20); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3419 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3420 | MCHBAR16(0x31c + (channel << 10)) = 0x101; |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 3421 | MCHBAR16(0x360 + (channel << 10)) = 0x909; |
| 3422 | MCHBAR16(0x3a4 + (channel << 10)) = 0x101; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3423 | MCHBAR16(0x3e8 + (channel << 10)) = 0x101; |
| 3424 | MCHBAR32(0x320 + (channel << 10)) = 0x29002900; |
| 3425 | MCHBAR32(0x324 + (channel << 10)) = 0x0; |
| 3426 | MCHBAR32(0x368 + (channel << 10)) = 0x32003200; |
| 3427 | MCHBAR16(0x352 + (channel << 10)) = 0x505; |
| 3428 | MCHBAR16(0x354 + (channel << 10)) = 0x3c3c; |
| 3429 | MCHBAR16(0x356 + (channel << 10)) = 0x1040; |
| 3430 | MCHBAR16(0x39a + (channel << 10)) = 0x73e4; |
| 3431 | MCHBAR16(0x3de + (channel << 10)) = 0x77ed; |
| 3432 | MCHBAR16(0x422 + (channel << 10)) = 0x1040; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3433 | } |
| 3434 | |
| 3435 | write_1d0(0x4, 0x151, 4, 1); |
| 3436 | write_1d0(0, 0x142, 3, 1); |
| 3437 | rdmsr(0x1ac); // !!!! |
| 3438 | write_500(&info, 1, 1, 0x6b3, 4, 1); |
| 3439 | write_500(&info, 1, 1, 0x6cf, 4, 1); |
| 3440 | |
Angel Pons | 244f455 | 2021-01-15 20:41:36 +0100 | [diff] [blame] | 3441 | rmw_1d0(0x21c, 0x38, 0, 6); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3442 | |
| 3443 | write_1d0(((!info.populated_ranks[1][0][0]) << 1) | ((!info. |
| 3444 | populated_ranks[0] |
| 3445 | [0][0]) << 0), |
| 3446 | 0x1d1, 3, 1); |
| 3447 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3448 | MCHBAR16(0x38e + (channel << 10)) = 0x5f5f; |
| 3449 | MCHBAR16(0x3d2 + (channel << 10)) = 0x5f5f; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3450 | } |
| 3451 | |
| 3452 | set_334(0); |
| 3453 | |
| 3454 | program_base_timings(&info); |
| 3455 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3456 | MCHBAR8_OR(0x5ff, 0x80); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3457 | |
| 3458 | write_1d0(0x2, 0x1d5, 2, 1); |
| 3459 | write_1d0(0x20, 0x166, 7, 1); |
| 3460 | write_1d0(0x0, 0xeb, 3, 1); |
| 3461 | write_1d0(0x0, 0xf3, 6, 1); |
| 3462 | |
Angel Pons | 3d35756 | 2021-01-16 14:46:45 +0100 | [diff] [blame] | 3463 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 3464 | u8 a = 0; |
| 3465 | if (info.populated_ranks[channel][0][1] && info.clock_speed_index > 1) |
| 3466 | a = 3; |
| 3467 | if (info.silicon_revision == 0 || info.silicon_revision == 1) |
| 3468 | a = 3; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3469 | |
Angel Pons | 3d35756 | 2021-01-16 14:46:45 +0100 | [diff] [blame] | 3470 | for (lane = 0; lane < 9; lane++) { |
| 3471 | const u16 addr = 0x125 + get_lane_offset(0, 0, lane); |
| 3472 | rmw_500(&info, channel, addr, 6, 0xf, a); |
| 3473 | } |
| 3474 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3475 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3476 | if (s3resume) { |
| 3477 | if (info.cached_training == NULL) { |
| 3478 | u32 reg32; |
| 3479 | printk(BIOS_ERR, |
| 3480 | "Couldn't find training data. Rebooting\n"); |
| 3481 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
| 3482 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
Elyes HAOUAS | d45f338 | 2019-04-28 18:04:35 +0200 | [diff] [blame] | 3483 | full_reset(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3484 | } |
| 3485 | int tm; |
| 3486 | info.training = *info.cached_training; |
| 3487 | for (tm = 0; tm < 4; tm++) |
| 3488 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 3489 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 3490 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 3491 | for (lane = 0; lane < 9; lane++) |
| 3492 | write_500(&info, |
| 3493 | channel, |
| 3494 | info.training. |
| 3495 | lane_timings |
| 3496 | [tm][channel] |
| 3497 | [slot][rank] |
| 3498 | [lane], |
| 3499 | get_timing_register_addr |
| 3500 | (lane, tm, |
| 3501 | slot, rank), |
| 3502 | 9, 0); |
| 3503 | write_1d0(info.cached_training->reg_178, 0x178, 7, 1); |
| 3504 | write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); |
| 3505 | } |
| 3506 | |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3507 | MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3508 | MCHBAR32(0x1f0) = 0x1d000200; |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3509 | MCHBAR8_OR(0x1f0, 0x1); |
| 3510 | while (MCHBAR8(0x1f0) & 1) |
| 3511 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3512 | |
| 3513 | program_board_delay(&info); |
| 3514 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3515 | MCHBAR8(0x5ff) = 0x0; |
| 3516 | MCHBAR8(0x5ff) = 0x80; |
| 3517 | MCHBAR8(0x5f4) = 0x1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3518 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3519 | MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ? |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 3520 | while (MCHBAR32(0x130) & 1) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3521 | ; |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3522 | |
| 3523 | rmw_1d0(0x14b, 0x47, 0x30, 7); |
| 3524 | rmw_1d0(0xd6, 0x38, 7, 6); |
| 3525 | rmw_1d0(0x328, 0x38, 7, 6); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3526 | |
| 3527 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Angel Pons | c10f8b2 | 2021-01-15 20:34:51 +0100 | [diff] [blame] | 3528 | set_4cf(&info, channel, 1, 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3529 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3530 | rmw_1d0(0x116, 0xe, 0, 4); |
| 3531 | rmw_1d0(0xae, 0x3e, 0, 6); |
| 3532 | rmw_1d0(0x300, 0x3e, 0, 6); |
| 3533 | MCHBAR16_AND(0x356, 0x7fff); |
| 3534 | MCHBAR16_AND(0x756, 0x7fff); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3535 | MCHBAR32_AND(0x140, ~0x07000000); |
| 3536 | MCHBAR32_AND(0x138, ~0x07000000); |
| 3537 | MCHBAR32(0x130) = 0x31111301; |
Vladimir Serbinenko | 25fc532 | 2014-12-07 13:05:44 +0100 | [diff] [blame] | 3538 | /* Wait until REG130b0 is 1. */ |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 3539 | while (MCHBAR32(0x130) & 1) |
Vladimir Serbinenko | 25fc532 | 2014-12-07 13:05:44 +0100 | [diff] [blame] | 3540 | ; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3541 | |
Angel Pons | 2668191 | 2021-01-15 21:36:28 +0100 | [diff] [blame] | 3542 | u8 value_a1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3543 | { |
Angel Pons | 2668191 | 2021-01-15 21:36:28 +0100 | [diff] [blame] | 3544 | const u8 val_xa1 = get_bits_420(read_1d0(0xa1, 6)); // = 0x1cf4040 // !!!! |
| 3545 | const u8 val_2f3 = get_bits_420(read_1d0(0x2f3, 6)); // = 0x10a4040 // !!!! |
| 3546 | value_a1 = val_xa1; |
| 3547 | rmw_1d0(0x320, 0x38, val_2f3, 6); |
| 3548 | rmw_1d0(0x14b, 0x78, val_xa1, 7); |
| 3549 | rmw_1d0(0xce, 0x38, val_xa1, 6); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3550 | } |
| 3551 | |
| 3552 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Angel Pons | c10f8b2 | 2021-01-15 20:34:51 +0100 | [diff] [blame] | 3553 | set_4cf(&info, channel, 1, 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3554 | |
Angel Pons | 244f455 | 2021-01-15 20:41:36 +0100 | [diff] [blame] | 3555 | rmw_1d0(0x116, 0xe, 1, 4); // = 0x4040432 // !!!! |
Angel Pons | 2668191 | 2021-01-15 21:36:28 +0100 | [diff] [blame] | 3556 | { |
| 3557 | if ((MCHBAR32(0x144) & 0x1f) < 0x13) |
| 3558 | value_a1 += 2; |
| 3559 | else |
| 3560 | value_a1 += 1; |
| 3561 | |
| 3562 | if (value_a1 > 7) |
| 3563 | value_a1 = 7; |
| 3564 | |
| 3565 | write_1d0(2, 0xae, 6, 1); |
| 3566 | write_1d0(2, 0x300, 6, 1); |
| 3567 | write_1d0(value_a1, 0x121, 3, 1); |
| 3568 | rmw_1d0(0xd6, 0x38, 4, 6); |
| 3569 | rmw_1d0(0x328, 0x38, 4, 6); |
| 3570 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3571 | |
| 3572 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Angel Pons | c10f8b2 | 2021-01-15 20:34:51 +0100 | [diff] [blame] | 3573 | set_4cf(&info, channel, 2, 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3574 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3575 | MCHBAR32(0x130) = 0x11111301 | (info.populated_ranks[1][0][0] << 30) | |
| 3576 | (info.populated_ranks[0][0][0] << 29); |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 3577 | while (MCHBAR8(0x130) & 1) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3578 | ; |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3579 | |
| 3580 | { |
Angel Pons | 2668191 | 2021-01-15 21:36:28 +0100 | [diff] [blame] | 3581 | const u8 val_xa1 = get_bits_420(read_1d0(0xa1, 6)); |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3582 | read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! |
| 3583 | rmw_1d0(0x21c, 0x38, 0, 6); |
Angel Pons | 2668191 | 2021-01-15 21:36:28 +0100 | [diff] [blame] | 3584 | rmw_1d0(0x14b, 0x78, val_xa1, 7); |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3585 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3586 | |
| 3587 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Angel Pons | c10f8b2 | 2021-01-15 20:34:51 +0100 | [diff] [blame] | 3588 | set_4cf(&info, channel, 2, 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3589 | |
| 3590 | set_334(1); |
| 3591 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3592 | MCHBAR8(0x1e8) = 0x4; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3593 | |
| 3594 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
| 3595 | write_500(&info, channel, |
| 3596 | 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2, |
| 3597 | 1); |
| 3598 | write_500(&info, channel, 0x3, 0x69b, 2, 1); |
| 3599 | } |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3600 | MCHBAR32_AND_OR(0x2d0, 0xff2c01ff, 0x200000); |
| 3601 | MCHBAR16(0x6c0) = 0x14a0; |
| 3602 | MCHBAR32_AND_OR(0x6d0, 0xff0080ff, 0x8000); |
| 3603 | MCHBAR16(0x232) = 0x8; |
| 3604 | /* 0x40004 or 0 depending on ? */ |
| 3605 | MCHBAR32_AND_OR(0x234, 0xfffbfffb, 0x40004); |
| 3606 | MCHBAR32_AND_OR(0x34, 0xfffffffd, 5); |
| 3607 | MCHBAR32(0x128) = 0x2150d05; |
| 3608 | MCHBAR8(0x12c) = 0x1f; |
| 3609 | MCHBAR8(0x12d) = 0x56; |
| 3610 | MCHBAR8(0x12e) = 0x31; |
| 3611 | MCHBAR8(0x12f) = 0x0; |
| 3612 | MCHBAR8(0x271) = 0x2; |
| 3613 | MCHBAR8(0x671) = 0x2; |
| 3614 | MCHBAR8(0x1e8) = 0x4; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3615 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3616 | MCHBAR32(0x294 + (channel << 10)) = |
| 3617 | (info.populated_ranks_mask[channel] & 3) << 16; |
| 3618 | MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000); |
| 3619 | MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3620 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 3621 | MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 | |
| 3622 | ((info.populated_ranks_mask[channel] & 3) << 20)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3623 | |
| 3624 | if (!s3resume) |
| 3625 | jedec_init(&info); |
| 3626 | |
| 3627 | int totalrank = 0; |
| 3628 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 3629 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 3630 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 3631 | if (info.populated_ranks[channel][slot][rank]) { |
| 3632 | jedec_read(&info, channel, slot, rank, |
| 3633 | totalrank, 0xa, 0x400); |
| 3634 | totalrank++; |
| 3635 | } |
| 3636 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3637 | MCHBAR8(0x12c) = 0x9f; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3638 | |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3639 | MCHBAR8_AND_OR(0x271, 0xcf, 0xe); |
| 3640 | MCHBAR8_AND_OR(0x671, 0xcf, 0xe); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3641 | |
| 3642 | if (!s3resume) { |
| 3643 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3644 | MCHBAR32(0x294 + (channel << 10)) = |
| 3645 | (info.populated_ranks_mask[channel] & 3) << 16; |
| 3646 | MCHBAR16(0x298 + (channel << 10)) = |
| 3647 | info.populated_ranks[channel][0][0] | |
| 3648 | (info.populated_ranks[channel][0][1] << 5); |
| 3649 | MCHBAR32(0x29c + (channel << 10)) = 0x77a; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3650 | } |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3651 | MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3652 | |
| 3653 | { |
| 3654 | u8 a, b; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3655 | a = MCHBAR8(0x243); |
| 3656 | b = MCHBAR8(0x643); |
| 3657 | MCHBAR8(0x243) = a | 2; |
| 3658 | MCHBAR8(0x643) = b | 2; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3659 | } |
| 3660 | |
| 3661 | write_1d0(7, 0x19b, 3, 1); |
| 3662 | write_1d0(7, 0x1c0, 3, 1); |
| 3663 | write_1d0(4, 0x1c6, 4, 1); |
| 3664 | write_1d0(4, 0x1cc, 4, 1); |
Angel Pons | c627dc9 | 2020-09-22 17:06:44 +0200 | [diff] [blame] | 3665 | rmw_1d0(0x151, 0xf, 0x4, 4); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3666 | MCHBAR32(0x584) = 0xfffff; |
| 3667 | MCHBAR32(0x984) = 0xfffff; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3668 | |
| 3669 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 3670 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 3671 | for (rank = 0; rank < NUM_RANKS; rank++) |
| 3672 | if (info. |
| 3673 | populated_ranks[channel][slot] |
| 3674 | [rank]) |
| 3675 | config_rank(&info, s3resume, |
| 3676 | channel, slot, |
| 3677 | rank); |
| 3678 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3679 | MCHBAR8(0x243) = 0x1; |
| 3680 | MCHBAR8(0x643) = 0x1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3681 | } |
| 3682 | |
| 3683 | /* was == 1 but is common */ |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3684 | pci_write_config16(NORTHBRIDGE, 0xc8, 3); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3685 | write_26c(0, 0x820); |
| 3686 | write_26c(1, 0x820); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3687 | MCHBAR32_OR(0x130, 2); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3688 | /* end */ |
| 3689 | |
| 3690 | if (s3resume) { |
| 3691 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3692 | MCHBAR32(0x294 + (channel << 10)) = |
| 3693 | (info.populated_ranks_mask[channel] & 3) << 16; |
| 3694 | MCHBAR16(0x298 + (channel << 10)) = |
| 3695 | info.populated_ranks[channel][0][0] | |
| 3696 | (info.populated_ranks[channel][0][1] << 5); |
| 3697 | MCHBAR32(0x29c + (channel << 10)) = 0x77a; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3698 | } |
Felix Held | f83d80b | 2018-07-29 05:30:30 +0200 | [diff] [blame] | 3699 | MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3700 | } |
| 3701 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3702 | MCHBAR32_AND(0xfa4, ~0x01000002); |
| 3703 | MCHBAR32(0xfb0) = 0x2000e019; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3704 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3705 | /* Before training. */ |
| 3706 | timestamp_add_now(103); |
| 3707 | |
| 3708 | if (!s3resume) |
| 3709 | ram_training(&info); |
| 3710 | |
| 3711 | /* After training. */ |
Paul Menzel | 9e817bf | 2015-05-28 07:32:48 +0200 | [diff] [blame] | 3712 | timestamp_add_now(104); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3713 | |
| 3714 | dump_timings(&info); |
| 3715 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3716 | program_modules_memory_map(&info, 0); |
| 3717 | program_total_memory_map(&info); |
| 3718 | |
| 3719 | if (info.non_interleaved_part_mb != 0 && info.interleaved_part_mb != 0) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3720 | MCHBAR8(0x111) = 0x20 | (0 << 2) | (1 << 6) | (0 << 7); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3721 | else if (have_match_ranks(&info, 0, 4) && have_match_ranks(&info, 1, 4)) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3722 | MCHBAR8(0x111) = 0x20 | (3 << 2) | (0 << 6) | (1 << 7); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3723 | else if (have_match_ranks(&info, 0, 2) && have_match_ranks(&info, 1, 2)) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3724 | MCHBAR8(0x111) = 0x20 | (3 << 2) | (0 << 6) | (0 << 7); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3725 | else |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3726 | MCHBAR8(0x111) = 0x20 | (3 << 2) | (1 << 6) | (0 << 7); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3727 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3728 | MCHBAR32_AND(0xfac, ~0x80000000); |
| 3729 | MCHBAR32(0xfb4) = 0x4800; |
| 3730 | MCHBAR32(0xfb8) = (info.revision < 8) ? 0x20 : 0x0; |
| 3731 | MCHBAR32(0xe94) = 0x7ffff; |
| 3732 | MCHBAR32(0xfc0) = 0x80002040; |
| 3733 | MCHBAR32(0xfc4) = 0x701246; |
| 3734 | MCHBAR8_AND(0xfc8, ~0x70); |
| 3735 | MCHBAR32_OR(0xe5c, 0x1000000); |
| 3736 | MCHBAR32_AND_OR(0x1a70, ~0x00100000, 0x00200000); |
| 3737 | MCHBAR32(0x50) = 0x700b0; |
| 3738 | MCHBAR32(0x3c) = 0x10; |
| 3739 | MCHBAR8(0x1aa8) = (MCHBAR8(0x1aa8) & ~0x35) | 0xa; |
| 3740 | MCHBAR8_OR(0xff4, 0x2); |
| 3741 | MCHBAR32_AND_OR(0xff8, ~0xe008, 0x1020); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3742 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3743 | MCHBAR32(0xd00) = IOMMU_BASE2 | 1; |
| 3744 | MCHBAR32(0xd40) = IOMMU_BASE1 | 1; |
| 3745 | MCHBAR32(0xdc0) = IOMMU_BASE4 | 1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3746 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 3747 | write32p(IOMMU_BASE1 | 0xffc, 0x80000000); |
| 3748 | write32p(IOMMU_BASE2 | 0xffc, 0xc0000000); |
| 3749 | write32p(IOMMU_BASE4 | 0xffc, 0x80000000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3750 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3751 | { |
| 3752 | u32 eax; |
| 3753 | |
| 3754 | eax = info.fsb_frequency / 9; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3755 | MCHBAR32_AND_OR(0xfcc, 0xfffc0000, |
| 3756 | (eax * 0x280) | (eax * 0x5000) | eax | 0x40000); |
| 3757 | MCHBAR32(0x20) = 0x33001; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3758 | } |
| 3759 | |
| 3760 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3761 | MCHBAR32_AND(0x220 + (channel << 10), ~0x7770); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3762 | if (info.max_slots_used_in_channel == 1) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3763 | MCHBAR16_OR(0x237 + (channel << 10), 0x0201); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3764 | else |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3765 | MCHBAR16_AND(0x237 + (channel << 10), ~0x0201); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3766 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3767 | MCHBAR8_OR(0x241 + (channel << 10), 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3768 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3769 | if (info.clock_speed_index <= 1 && (info.silicon_revision == 2 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3770 | || info.silicon_revision == 3)) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3771 | MCHBAR32_OR(0x248 + (channel << 10), 0x00102000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3772 | else |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3773 | MCHBAR32_AND(0x248 + (channel << 10), ~0x00102000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3774 | } |
| 3775 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3776 | MCHBAR32_OR(0x115, 0x1000000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3777 | |
| 3778 | { |
| 3779 | u8 al; |
| 3780 | al = 0xd; |
| 3781 | if (!(info.silicon_revision == 0 || info.silicon_revision == 1)) |
| 3782 | al += 2; |
| 3783 | al |= ((1 << (info.max_slots_used_in_channel - 1)) - 1) << 4; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3784 | MCHBAR32(0x210) = (al << 16) | 0x20; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3785 | } |
| 3786 | |
| 3787 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3788 | MCHBAR32(0x288 + (channel << 10)) = 0x70605040; |
| 3789 | MCHBAR32(0x28c + (channel << 10)) = 0xfffec080; |
| 3790 | MCHBAR32(0x290 + (channel << 10)) = 0x282091c | |
| 3791 | ((info.max_slots_used_in_channel - 1) << 0x16); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3792 | } |
| 3793 | u32 reg1c; |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3794 | pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK |
Angel Pons | 3b264d0 | 2020-09-15 00:25:49 +0200 | [diff] [blame] | 3795 | reg1c = EPBAR32(EPVC1RCAP); // = 0x8001 // OK |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3796 | pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK |
Angel Pons | 3b264d0 | 2020-09-15 00:25:49 +0200 | [diff] [blame] | 3797 | EPBAR32(EPVC1RCAP) = reg1c; // OK |
Elyes HAOUAS | 97642c2 | 2019-05-22 20:53:25 +0200 | [diff] [blame] | 3798 | MCHBAR8(0xe08); // = 0x0 |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3799 | pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3800 | MCHBAR8_OR(0x1210, 2); |
| 3801 | MCHBAR32(0x1200) = 0x8800440; |
| 3802 | MCHBAR32(0x1204) = 0x53ff0453; |
| 3803 | MCHBAR32(0x1208) = 0x19002043; |
| 3804 | MCHBAR16(0x1214) = 0x320; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3805 | |
| 3806 | if (info.revision == 0x10 || info.revision == 0x11) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3807 | MCHBAR16(0x1214) = 0x220; |
| 3808 | MCHBAR8_OR(0x1210, 0x40); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3809 | } |
| 3810 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3811 | MCHBAR8_OR(0x1214, 0x4); |
| 3812 | MCHBAR8(0x120c) = 0x1; |
| 3813 | MCHBAR8(0x1218) = 0x3; |
| 3814 | MCHBAR8(0x121a) = 0x3; |
| 3815 | MCHBAR8(0x121c) = 0x3; |
| 3816 | MCHBAR16(0xc14) = 0x0; |
| 3817 | MCHBAR16(0xc20) = 0x0; |
| 3818 | MCHBAR32(0x1c) = 0x0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3819 | |
| 3820 | /* revision dependent here. */ |
| 3821 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3822 | MCHBAR16_OR(0x1230, 0x1f07); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3823 | |
| 3824 | if (info.uma_enabled) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3825 | MCHBAR32_OR(0x11f4, 0x10000000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3826 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3827 | MCHBAR16_OR(0x1230, 0x8000); |
| 3828 | MCHBAR8_OR(0x1214, 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3829 | |
| 3830 | u8 bl, ebpb; |
| 3831 | u16 reg_1020; |
| 3832 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3833 | reg_1020 = MCHBAR32(0x1020); // = 0x6c733c // OK |
| 3834 | MCHBAR8(0x1070) = 0x1; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3835 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3836 | MCHBAR32(0x1000) = 0x100; |
| 3837 | MCHBAR8(0x1007) = 0x0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3838 | |
| 3839 | if (reg_1020 != 0) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3840 | MCHBAR16(0x1018) = 0x0; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3841 | bl = reg_1020 >> 8; |
| 3842 | ebpb = reg_1020 & 0xff; |
| 3843 | } else { |
| 3844 | ebpb = 0; |
| 3845 | bl = 8; |
| 3846 | } |
| 3847 | |
| 3848 | rdmsr(0x1a2); |
| 3849 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3850 | MCHBAR32(0x1014) = 0xffffffff; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3851 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3852 | MCHBAR32(0x1010) = ((((ebpb + 0x7d) << 7) / bl) & 0xff) * (!!reg_1020); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3853 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3854 | MCHBAR8(0x101c) = 0xb8; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3855 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3856 | MCHBAR8(0x123e) = (MCHBAR8(0x123e) & 0xf) | 0x60; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3857 | if (reg_1020 != 0) { |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3858 | MCHBAR32_AND_OR(0x123c, ~0x00900000, 0x600000); |
| 3859 | MCHBAR8(0x101c) = 0xb8; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3860 | } |
| 3861 | |
| 3862 | setup_heci_uma(&info); |
| 3863 | |
| 3864 | if (info.uma_enabled) { |
| 3865 | u16 ax; |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3866 | MCHBAR32_OR(0x11b0, 0x4000); |
| 3867 | MCHBAR32_OR(0x11b4, 0x4000); |
| 3868 | MCHBAR16_OR(0x1190, 0x4000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3869 | |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3870 | ax = MCHBAR16(0x1190) & 0xf00; // = 0x480a // OK |
| 3871 | MCHBAR16(0x1170) = ax | (MCHBAR16(0x1170) & 0x107f) | 0x4080; |
| 3872 | MCHBAR16_OR(0x1170, 0x1000); |
| 3873 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3874 | udelay(1000); |
Felix Held | 29a9c07 | 2018-07-29 01:34:45 +0200 | [diff] [blame] | 3875 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3876 | u16 ecx; |
Felix Held | 22ca8cb | 2018-07-29 05:09:44 +0200 | [diff] [blame] | 3877 | for (ecx = 0xffff; ecx && (MCHBAR16(0x1170) & 0x1000); ecx--) |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3878 | ; |
| 3879 | MCHBAR16_AND(0x1190, ~0x4000); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3880 | } |
| 3881 | |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 3882 | pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, |
| 3883 | pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3884 | udelay(10000); |
Felix Held | 04be2dd | 2018-07-29 04:53:22 +0200 | [diff] [blame] | 3885 | MCHBAR16(0x2ca8) = 0x8; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3886 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3887 | udelay(1000); |
| 3888 | dump_timings(&info); |
Vladimir Serbinenko | b16f092 | 2014-06-07 16:27:27 +0200 | [diff] [blame] | 3889 | cbmem_wasnot_inited = cbmem_recovery(s3resume); |
| 3890 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3891 | if (!s3resume) |
| 3892 | save_timings(&info); |
Vladimir Serbinenko | b16f092 | 2014-06-07 16:27:27 +0200 | [diff] [blame] | 3893 | if (s3resume && cbmem_wasnot_inited) { |
Vladimir Serbinenko | b16f092 | 2014-06-07 16:27:27 +0200 | [diff] [blame] | 3894 | printk(BIOS_ERR, "Failed S3 resume.\n"); |
Kyösti Mälkki | e1aa983 | 2019-03-23 10:00:31 +0200 | [diff] [blame] | 3895 | ram_check_nodie(1 * MiB); |
Vladimir Serbinenko | b16f092 | 2014-06-07 16:27:27 +0200 | [diff] [blame] | 3896 | |
Vladimir Serbinenko | b16f092 | 2014-06-07 16:27:27 +0200 | [diff] [blame] | 3897 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | d45f338 | 2019-04-28 18:04:35 +0200 | [diff] [blame] | 3898 | full_reset(); |
Vladimir Serbinenko | b16f092 | 2014-06-07 16:27:27 +0200 | [diff] [blame] | 3899 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3900 | } |