commit 9addda3c410041ea93ae5587d17460da9a9c312f
author Angel Pons <th3fanbus@gmail.com> Wed Jul 22 18:37:32 2020 +0200
committer Patrick Georgi <pgeorgi@google.com> Mon Aug 03 05:32:20 2020 +0000
tree 5579f274b2d7e801b819d5711ddbdf96414101c0
parent c642a0d8942735b393040b877769f1d4a3a9ebe8

nb/intel/ironlake: Add Generic Non-Core register definitions

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/ironlake/raminit.c

diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 81a7727..dd1dbd0 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3955,8 +3955,8 @@
 	pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS);	// !!!!
 	pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555);
 	pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS);	// !!!!
-	pci_read_config32(QPI_NON_CORE, 0xd0);	// !!!!
-	pci_write_config32(QPI_NON_CORE, 0xd0, 0x180);
+	pci_read_config32(QPI_NON_CORE, MIRROR_PORT_CTL);	// !!!!
+	pci_write_config32(QPI_NON_CORE, MIRROR_PORT_CTL, 0x180);
 	gav(MCHBAR32(0x1af0));	// !!!!
 	gav(MCHBAR32(0x1af0));	// !!!!
 	MCHBAR32(0x1af0) = 0x1f020003;
@@ -4225,7 +4225,7 @@
 
 	MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8);
 	MCHBAR32_AND_OR(0x2c80, 0, 0x53688);	// !!!!
-	pci_write_config32(QPI_NON_CORE, 0x60, 0x20220);
+	pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220);
 	MCHBAR16(0x2c20);	// !!!!
 	MCHBAR16(0x2c10);	// !!!!
 	MCHBAR16(0x2c00);	// !!!!