nb/intel/nehalem: use pmclib to detect S3 resume
During the raminit the CPU gets reset, so reprogram those bits in
PM1_CNT such that the CPU remains aware that this is a S3 resume path
after the reset.
Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 4618911..c887de1 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -36,6 +36,7 @@
#include <cpu/intel/turbo.h>
#include <mrc_cache.h>
#include <southbridge/intel/ibexpeak/me.h>
+#include <southbridge/intel/common/pmbase.h>
#include <delay.h>
#include <types.h>
@@ -4246,6 +4247,11 @@
MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"?
/* This issues a CPU reset without resetting the platform */
printk(BIOS_DEBUG, "Issuing a CPU reset\n");
+ /* Write back the S3 state to PM1_CNT to let the reset CPU
+ know it also needs to take the s3 path. */
+ if (s3resume)
+ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT)
+ | (SLP_TYP_S3 << 10));
MCHBAR32_OR(0x1af0, 0x10);
halt();
}