commit 3b264d00745cfb1deca560ea6c491632dd79835f
author Angel Pons <th3fanbus@gmail.com> Tue Sep 15 00:25:49 2020 +0200
committer Angel Pons <th3fanbus@gmail.com> Sat Oct 10 19:30:56 2020 +0000
tree d78eae00104411d534330ed1b7d36bba13af9fc7
parent b0e169ac854d74fe267c00eb160c482c7d5e6dfd

nb/intel/ironlake: Clean up DMIBAR/EPBAR registers

Several registers have been copy-pasted from i945 and do not exist on
Ironlake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/ironlake/raminit.c

diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index dfe9853..05323f1 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1810,20 +1810,20 @@
 
 	pci_read_config32(NORTHBRIDGE, DMIBAR);
 	if (info->memory_reserved_for_heci_mb) {
-		DMIBAR32(0x14) &= ~0x80;
+		DMIBAR32(DMIVC0RCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x14, read32(DEFAULT_RCBA   + 0x14) & ~0x80);
-		DMIBAR32(0x20) &= ~0x80;
+		DMIBAR32(DMIVC1RCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x20, read32(DEFAULT_RCBA   + 0x20) & ~0x80);
-		DMIBAR32(0x2c) &= ~0x80;
+		DMIBAR32(DMIVCPRCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x30, read32(DEFAULT_RCBA   + 0x30) & ~0x80);
-		DMIBAR32(0x38) &= ~0x80;
+		DMIBAR32(DMIVCMRCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x40, read32(DEFAULT_RCBA   + 0x40) & ~0x80);
 
 		write32(DEFAULT_RCBA   + 0x40, 0x87000080);	// OK
-		DMIBAR32(0x38) = 0x87000080;	// OK
+		DMIBAR32(DMIVCMRCTL) = 0x87000080;	// OK
 
 		while ((read16(DEFAULT_RCBA + 0x46) & 2) &&
-			DMIBAR16(0x3e) & 2)
+			DMIBAR16(DMIVCMRSTS) & VCMNP)
 			;
 	}
 
@@ -4600,9 +4600,9 @@
 	}
 	u32 reg1c;
 	pci_read_config32(NORTHBRIDGE, 0x40);	// = DEFAULT_EPBAR | 0x001 // OK
-	reg1c = EPBAR32(0x01c);	// = 0x8001 // OK
+	reg1c = EPBAR32(EPVC1RCAP);	// = 0x8001 // OK
 	pci_read_config32(NORTHBRIDGE, 0x40);	// = DEFAULT_EPBAR | 0x001 // OK
-	EPBAR32(0x01c) = reg1c;	// OK
+	EPBAR32(EPVC1RCAP) = reg1c;	// OK
 	MCHBAR8(0xe08);	// = 0x0
 	pci_read_config32(NORTHBRIDGE, 0xe4);	// = 0x316126
 	MCHBAR8_OR(0x1210, 2);