Elyes HAOUAS | 8741510 | 2020-05-07 11:49:08 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 2 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 3 | config SOUTHBRIDGE_AMD_CIMX_SB800 |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 4 | bool |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 5 | default n |
Kyösti Mälkki | 8526c3a | 2014-01-03 08:20:50 +0200 | [diff] [blame] | 6 | select HAVE_USBDEBUG_OPTIONS |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 7 | select AMD_SB_CIMX |
Nico Huber | 3e1b3b1 | 2018-10-07 12:45:47 +0200 | [diff] [blame] | 8 | select HAVE_CF9_RESET |
| 9 | select HAVE_CF9_RESET_PREPARE |
Michał Żygowski | 2317b4f | 2019-11-28 12:59:44 +0100 | [diff] [blame] | 10 | select SOC_AMD_COMMON |
Michał Żygowski | 2317b4f | 2019-11-28 12:59:44 +0100 | [diff] [blame] | 11 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | 3136424 | 2021-07-23 19:18:02 +0200 | [diff] [blame] | 12 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM |
Felix Held | 21cdf0d | 2020-11-23 16:24:29 +0100 | [diff] [blame] | 13 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 14 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 15 | if SOUTHBRIDGE_AMD_CIMX_SB800 |
Kerry Sheh | d7e856b9 | 2011-10-11 17:27:06 +0800 | [diff] [blame] | 16 | config ENABLE_IDE_COMBINED_MODE |
| 17 | bool "Enable SATA IDE combined mode" |
| 18 | default n |
| 19 | help |
| 20 | If Combined Mode is enabled. IDE controller is exposed and |
| 21 | SATA controller has control over Port0 through Port3, |
| 22 | IDE controller has control over Port4 and Port5. |
| 23 | |
| 24 | If Combined Mode is disabled, IDE controller is hidden and |
| 25 | SATA controller has full control of all 6 Ports when operating in non-IDE mode. |
| 26 | |
| 27 | config IDE_COMBINED_MODE |
| 28 | hex |
Martin Roth | 3b87812 | 2016-09-30 14:43:01 -0600 | [diff] [blame] | 29 | default 0x0 if ENABLE_IDE_COMBINED_MODE |
| 30 | default 0x1 if !ENABLE_IDE_COMBINED_MODE |
Kerry Sheh | d7e856b9 | 2011-10-11 17:27:06 +0800 | [diff] [blame] | 31 | |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 32 | choice |
| 33 | prompt "SATA Mode" |
Paul Menzel | ee5c111 | 2013-03-12 12:41:40 +0100 | [diff] [blame] | 34 | default SB800_SATA_AHCI |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 35 | help |
| 36 | Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. |
Paul Menzel | bae3f06 | 2013-03-28 13:03:38 +0100 | [diff] [blame] | 37 | The default is AHCI. |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 38 | |
| 39 | config SB800_SATA_IDE |
| 40 | bool "NATIVE" |
| 41 | help |
Paul Menzel | bae3f06 | 2013-03-28 13:03:38 +0100 | [diff] [blame] | 42 | NATIVE does not require a ROM. |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 43 | |
| 44 | config SB800_SATA_AHCI |
| 45 | bool "AHCI" |
| 46 | help |
Paul Menzel | bae3f06 | 2013-03-28 13:03:38 +0100 | [diff] [blame] | 47 | AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 48 | For example, seabios does not require the AHCI ROM. |
| 49 | |
| 50 | config SB800_SATA_RAID |
| 51 | bool "RAID" |
| 52 | help |
| 53 | sb800 RAID mode must have the two required ROM files. |
| 54 | |
| 55 | endchoice |
| 56 | |
| 57 | config SB800_SATA_MODE |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 58 | hex |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 59 | depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) |
Martin Roth | 3b87812 | 2016-09-30 14:43:01 -0600 | [diff] [blame] | 60 | default 0x0 if SB800_SATA_IDE |
| 61 | default 0x1 if SB800_SATA_RAID |
| 62 | default 0x2 if SB800_SATA_AHCI |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 63 | |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 64 | config SB_SUPERIO_HWM |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 65 | bool |
| 66 | default n |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 67 | |
| 68 | if SB800_SATA_AHCI |
| 69 | config AHCI_ROM_ID |
| 70 | string "AHCI device PCI IDs" |
| 71 | default "1002,4391" |
| 72 | |
| 73 | config SB800_AHCI_ROM |
| 74 | bool "Add a AHCI ROM" |
| 75 | |
| 76 | config AHCI_ROM_FILE |
| 77 | string "AHCI ROM path and filename" |
| 78 | depends on SB800_AHCI_ROM |
| 79 | default "site-local/sb800/ahci.bin" |
| 80 | endif |
| 81 | |
| 82 | if SB800_SATA_RAID |
| 83 | config RAID_ROM_ID |
| 84 | string "RAID device PCI IDs" |
| 85 | default "1002,4393" |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 86 | help |
| 87 | 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 88 | |
| 89 | config RAID_ROM_FILE |
| 90 | string "RAID ROM path and filename" |
| 91 | depends on SB800_SATA_RAID |
| 92 | default "site-local/sb800/raid.bin" |
| 93 | |
| 94 | config RAID_MISC_ROM_FILE |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 95 | string "RAID Misc ROM path and filename" |
| 96 | default "site-local/sb800/misc.bin" |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 97 | depends on SB800_SATA_RAID |
| 98 | |
Kerry Sheh | 55437c5 | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 99 | config RAID_MISC_ROM_POSITION |
| 100 | hex "RAID Misc ROM Position" |
| 101 | default 0xFFF00000 |
| 102 | depends on SB800_SATA_RAID |
| 103 | help |
| 104 | The RAID ROM requires that the MISC ROM is located between the range |
| 105 | 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. |
| 106 | The CONFIG_ROM_SIZE must larger than 0x100000. |
| 107 | |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 108 | endif |
| 109 | |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 110 | config SB800_IMC_FWM |
| 111 | bool "Add IMC firmware" |
| 112 | default n |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 113 | select SPI_FLASH_HAS_VOLATILE_GROUP if SPI_FLASH |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 114 | help |
| 115 | Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control. |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 116 | |
| 117 | if SB800_IMC_FWM |
| 118 | |
| 119 | config SB800_IMC_FWM_FILE |
| 120 | string "IMC firmware path and filename" |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 121 | default "3rdparty/blobs/southbridge/amd/sb800/imc.bin" |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 122 | |
| 123 | choice |
| 124 | prompt "SB800 Firmware ROM Position" |
| 125 | |
| 126 | config SB800_FWM_AT_FFFA0000 |
| 127 | bool "0xFFFA0000" |
| 128 | help |
| 129 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 130 | fixed locations in memory. The location used shouldn't matter, just |
| 131 | select an area that doesn't conflict with anything else. |
| 132 | |
| 133 | config SB800_FWM_AT_FFF20000 |
| 134 | bool "0xFFF20000" |
| 135 | help |
| 136 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 137 | fixed locations in memory. The location used shouldn't matter, just |
| 138 | select an area that doesn't conflict with anything else. |
| 139 | |
| 140 | config SB800_FWM_AT_FFE20000 |
| 141 | depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 || BOARD_ROMSIZE_KB_2048 |
| 142 | bool "0xFFE20000" |
| 143 | help |
| 144 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 145 | fixed locations in memory. The location used shouldn't matter, just |
| 146 | select an area that doesn't conflict with anything else. |
| 147 | |
| 148 | config SB800_FWM_AT_FFC20000 |
| 149 | depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 |
| 150 | bool "0xFFC20000" |
| 151 | help |
| 152 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 153 | fixed locations in memory. The location used shouldn't matter, just |
| 154 | select an area that doesn't conflict with anything else. |
| 155 | |
| 156 | config SB800_FWM_AT_FF820000 |
| 157 | depends on BOARD_ROMSIZE_KB_8192 |
| 158 | bool "0xFF820000" |
| 159 | help |
| 160 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 161 | fixed locations in memory. The location used shouldn't matter, just |
| 162 | select an area that doesn't conflict with anything else. |
| 163 | |
| 164 | endchoice |
| 165 | |
| 166 | config SB800_FWM_POSITION |
| 167 | hex |
| 168 | default 0xFFFA0000 if SB800_FWM_AT_FFFA0000 |
| 169 | default 0xFFF20000 if SB800_FWM_AT_FFF20000 |
| 170 | default 0xFFE20000 if SB800_FWM_AT_FFE20000 |
| 171 | default 0xFFC20000 if SB800_FWM_AT_FFC20000 |
Martin Roth | 238780c | 2013-01-08 13:46:50 -0700 | [diff] [blame] | 172 | default 0xFF820000 if SB800_FWM_AT_FF820000 |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 173 | |
| 174 | endif #SB800_IMC_FWM |
| 175 | |
Kyösti Mälkki | a9bbdd3 | 2013-08-09 02:24:05 +0300 | [diff] [blame] | 176 | config EHCI_BAR |
| 177 | hex |
| 178 | default 0xfef00000 |
| 179 | |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 180 | choice |
| 181 | prompt "Fan Control" |
| 182 | default SB800_NO_FAN_CONTROL |
| 183 | help |
| 184 | Select the method of SB800 fan control to be used. None would be |
| 185 | for either fixed maximum speed fans connected to the SB800 or for |
| 186 | an external chip controlling the fan speeds. Manual control sets |
| 187 | up the SB800 fan control registers. IMC fan control uses the SB800 |
| 188 | IMC to actively control the fan speeds. |
| 189 | |
| 190 | config SB800_NO_FAN_CONTROL |
| 191 | bool "None" |
| 192 | help |
| 193 | No SB800 Fan control - Do not set up the SB800 fan control registers. |
| 194 | |
| 195 | config SB800_MANUAL_FAN_CONTROL |
| 196 | bool "Manual" |
| 197 | help |
| 198 | Configure the SB800 fan control registers in devicetree.cb. |
| 199 | |
| 200 | config SB800_IMC_FAN_CONTROL |
| 201 | bool "IMC Based" |
| 202 | depends on SB800_IMC_FWM |
| 203 | help |
| 204 | Set up the SB800 to use the IMC based Fan controller. This requires |
Elyes HAOUAS | 1bcd7fc | 2016-07-28 21:20:04 +0200 | [diff] [blame] | 205 | the IMC ROM from AMD. Configure the registers in devicetree.cb. |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 206 | |
| 207 | endchoice |
| 208 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 209 | endif #SOUTHBRIDGE_AMD_CIMX_SB800 |