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Frank Vibrans63e62b02011-02-14 18:38:14 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Advanced Micro Devices, Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
efdesign9805a89ab2011-06-20 17:38:49 -070020config SOUTHBRIDGE_AMD_CIMX_SB800
Frank Vibrans63e62b02011-02-14 18:38:14 +000021 bool
Kerry Shefeed3292011-08-18 18:03:44 +080022 default n
Frank Vibrans63e62b02011-02-14 18:38:14 +000023 select IOAPIC
Kerry Shefeed3292011-08-18 18:03:44 +080024 select AMD_SB_CIMX
Frank Vibrans63e62b02011-02-14 18:38:14 +000025
efdesign9805a89ab2011-06-20 17:38:49 -070026if SOUTHBRIDGE_AMD_CIMX_SB800
Frank Vibrans63e62b02011-02-14 18:38:14 +000027config BOOTBLOCK_SOUTHBRIDGE_INIT
28 string
efdesign9805a89ab2011-06-20 17:38:49 -070029 default "southbridge/amd/cimx/sb800/bootblock.c"
Kerry She6209c822011-08-18 18:44:00 +080030
Kerry Shehd7e856b92011-10-11 17:27:06 +080031config ENABLE_IDE_COMBINED_MODE
32 bool "Enable SATA IDE combined mode"
33 default n
34 help
35 If Combined Mode is enabled. IDE controller is exposed and
36 SATA controller has control over Port0 through Port3,
37 IDE controller has control over Port4 and Port5.
38
39 If Combined Mode is disabled, IDE controller is hidden and
40 SATA controller has full control of all 6 Ports when operating in non-IDE mode.
41
42config IDE_COMBINED_MODE
43 hex
44 default "0x0" if ENABLE_IDE_COMBINED_MODE
45 default "0x1" if !ENABLE_IDE_COMBINED_MODE
46
Kerry Shehd4a0e7d2011-10-10 17:17:39 +080047choice
48 prompt "SATA Mode"
49 default SB800_SATA_IDE
50 help
51 Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
52 The default is NATIVE.
53
54config SB800_SATA_IDE
55 bool "NATIVE"
56 help
57 NATIVE is the default mode and does not require a ROM.
58
59config SB800_SATA_AHCI
60 bool "AHCI"
61 help
62 AHCI may work with or without AHCI ROM. It depends on the payload support.
63 For example, seabios does not require the AHCI ROM.
64
65config SB800_SATA_RAID
66 bool "RAID"
67 help
68 sb800 RAID mode must have the two required ROM files.
69
70endchoice
71
72config SB800_SATA_MODE
73 hex
74 depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
75 default "0x0" if SB800_SATA_IDE
76 default "0x1" if SB800_SATA_RAID
77 default "0x2" if SB800_SATA_AHCI
78
Kerry She6209c822011-08-18 18:44:00 +080079config SB_SUPERIO_HWM
80 bool
81 default n
Kerry Shehd4a0e7d2011-10-10 17:17:39 +080082
83if SB800_SATA_AHCI
84config AHCI_ROM_ID
85 string "AHCI device PCI IDs"
86 default "1002,4391"
87
88config SB800_AHCI_ROM
89 bool "Add a AHCI ROM"
90
91config AHCI_ROM_FILE
92 string "AHCI ROM path and filename"
93 depends on SB800_AHCI_ROM
94 default "site-local/sb800/ahci.bin"
95endif
96
97if SB800_SATA_RAID
98config RAID_ROM_ID
99 string "RAID device PCI IDs"
100 default "1002,4393"
101 help
102 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
103
104config RAID_ROM_FILE
105 string "RAID ROM path and filename"
106 depends on SB800_SATA_RAID
107 default "site-local/sb800/raid.bin"
108
109config RAID_MISC_ROM_FILE
110 string "RAID Misc ROM path and filename"
111 default "site-local/sb800/misc.bin"
112 depends on SB800_SATA_RAID
113
Kerry Sheh55437c52011-10-12 11:42:59 +0800114config RAID_MISC_ROM_POSITION
115 hex "RAID Misc ROM Position"
116 default 0xFFF00000
117 depends on SB800_SATA_RAID
118 help
119 The RAID ROM requires that the MISC ROM is located between the range
120 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
121 The CONFIG_ROM_SIZE must larger than 0x100000.
122
Kerry Shehd4a0e7d2011-10-10 17:17:39 +0800123endif
124
Zheng Baoeb1d39b2012-08-27 17:45:01 +0800125config S3_VOLATILE_POS
126 hex "S3 volatile storage position"
127 default 0xFFFF0000
128 depends on HAVE_ACPI_RESUME
129 help
130 For a system with S3 feature, the BIOS needs to save some data to
131 non-volitile storage at cold boot stage.
132
Martin Rothe899e512012-12-05 16:07:11 -0700133config SB800_IMC_FWM
134 bool "Add IMC firmware"
135 default n
136 help
137 Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
Martin Rothe899e512012-12-05 16:07:11 -0700138
139if SB800_IMC_FWM
140
141config SB800_IMC_FWM_FILE
142 string "IMC firmware path and filename"
143 default "3rdparty/southbridge/amd/sb800/imc.bin"
144
145choice
146 prompt "SB800 Firmware ROM Position"
147
148config SB800_FWM_AT_FFFA0000
149 bool "0xFFFA0000"
150 help
151 The IMC and GEC ROMs requires a 'signature' located at one of several
152 fixed locations in memory. The location used shouldn't matter, just
153 select an area that doesn't conflict with anything else.
154
155config SB800_FWM_AT_FFF20000
156 bool "0xFFF20000"
157 help
158 The IMC and GEC ROMs requires a 'signature' located at one of several
159 fixed locations in memory. The location used shouldn't matter, just
160 select an area that doesn't conflict with anything else.
161
162config SB800_FWM_AT_FFE20000
163 depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 || BOARD_ROMSIZE_KB_2048
164 bool "0xFFE20000"
165 help
166 The IMC and GEC ROMs requires a 'signature' located at one of several
167 fixed locations in memory. The location used shouldn't matter, just
168 select an area that doesn't conflict with anything else.
169
170config SB800_FWM_AT_FFC20000
171 depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096
172 bool "0xFFC20000"
173 help
174 The IMC and GEC ROMs requires a 'signature' located at one of several
175 fixed locations in memory. The location used shouldn't matter, just
176 select an area that doesn't conflict with anything else.
177
178config SB800_FWM_AT_FF820000
179 depends on BOARD_ROMSIZE_KB_8192
180 bool "0xFF820000"
181 help
182 The IMC and GEC ROMs requires a 'signature' located at one of several
183 fixed locations in memory. The location used shouldn't matter, just
184 select an area that doesn't conflict with anything else.
185
186endchoice
187
188config SB800_FWM_POSITION
189 hex
190 default 0xFFFA0000 if SB800_FWM_AT_FFFA0000
191 default 0xFFF20000 if SB800_FWM_AT_FFF20000
192 default 0xFFE20000 if SB800_FWM_AT_FFE20000
193 default 0xFFC20000 if SB800_FWM_AT_FFC20000
Martin Roth238780c2013-01-08 13:46:50 -0700194 default 0xFF820000 if SB800_FWM_AT_FF820000
Martin Rothe899e512012-12-05 16:07:11 -0700195
196endif #SB800_IMC_FWM
197
198choice
199 prompt "Fan Control"
200 default SB800_NO_FAN_CONTROL
201 help
202 Select the method of SB800 fan control to be used. None would be
203 for either fixed maximum speed fans connected to the SB800 or for
204 an external chip controlling the fan speeds. Manual control sets
205 up the SB800 fan control registers. IMC fan control uses the SB800
206 IMC to actively control the fan speeds.
207
208config SB800_NO_FAN_CONTROL
209 bool "None"
210 help
211 No SB800 Fan control - Do not set up the SB800 fan control registers.
212
213config SB800_MANUAL_FAN_CONTROL
214 bool "Manual"
215 help
216 Configure the SB800 fan control registers in devicetree.cb.
217
218config SB800_IMC_FAN_CONTROL
219 bool "IMC Based"
220 depends on SB800_IMC_FWM
221 help
222 Set up the SB800 to use the IMC based Fan controller. This requires
223 the IMC rom from AMD. Configure the registers in devicetree.cb.
224
225endchoice
226
efdesign9805a89ab2011-06-20 17:38:49 -0700227endif #SOUTHBRIDGE_AMD_CIMX_SB800
Frank Vibrans63e62b02011-02-14 18:38:14 +0000228