Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 18 | ## |
| 19 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 20 | config SOUTHBRIDGE_AMD_CIMX_SB800 |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 21 | bool |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 22 | default n |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 23 | select IOAPIC |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 24 | select AMD_SB_CIMX |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 25 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 26 | if SOUTHBRIDGE_AMD_CIMX_SB800 |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 27 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 28 | string |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 29 | default "southbridge/amd/cimx/sb800/bootblock.c" |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 30 | |
Kerry Sheh | d7e856b9 | 2011-10-11 17:27:06 +0800 | [diff] [blame] | 31 | config ENABLE_IDE_COMBINED_MODE |
| 32 | bool "Enable SATA IDE combined mode" |
| 33 | default n |
| 34 | help |
| 35 | If Combined Mode is enabled. IDE controller is exposed and |
| 36 | SATA controller has control over Port0 through Port3, |
| 37 | IDE controller has control over Port4 and Port5. |
| 38 | |
| 39 | If Combined Mode is disabled, IDE controller is hidden and |
| 40 | SATA controller has full control of all 6 Ports when operating in non-IDE mode. |
| 41 | |
| 42 | config IDE_COMBINED_MODE |
| 43 | hex |
| 44 | default "0x0" if ENABLE_IDE_COMBINED_MODE |
| 45 | default "0x1" if !ENABLE_IDE_COMBINED_MODE |
| 46 | |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 47 | choice |
| 48 | prompt "SATA Mode" |
Paul Menzel | ee5c111 | 2013-03-12 12:41:40 +0100 | [diff] [blame] | 49 | default SB800_SATA_AHCI |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 50 | help |
| 51 | Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. |
Paul Menzel | bae3f06 | 2013-03-28 13:03:38 +0100 | [diff] [blame^] | 52 | The default is AHCI. |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 53 | |
| 54 | config SB800_SATA_IDE |
| 55 | bool "NATIVE" |
| 56 | help |
Paul Menzel | bae3f06 | 2013-03-28 13:03:38 +0100 | [diff] [blame^] | 57 | NATIVE does not require a ROM. |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 58 | |
| 59 | config SB800_SATA_AHCI |
| 60 | bool "AHCI" |
| 61 | help |
Paul Menzel | bae3f06 | 2013-03-28 13:03:38 +0100 | [diff] [blame^] | 62 | AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 63 | For example, seabios does not require the AHCI ROM. |
| 64 | |
| 65 | config SB800_SATA_RAID |
| 66 | bool "RAID" |
| 67 | help |
| 68 | sb800 RAID mode must have the two required ROM files. |
| 69 | |
| 70 | endchoice |
| 71 | |
| 72 | config SB800_SATA_MODE |
| 73 | hex |
| 74 | depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) |
| 75 | default "0x0" if SB800_SATA_IDE |
| 76 | default "0x1" if SB800_SATA_RAID |
| 77 | default "0x2" if SB800_SATA_AHCI |
| 78 | |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 79 | config SB_SUPERIO_HWM |
| 80 | bool |
| 81 | default n |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 82 | |
| 83 | if SB800_SATA_AHCI |
| 84 | config AHCI_ROM_ID |
| 85 | string "AHCI device PCI IDs" |
| 86 | default "1002,4391" |
| 87 | |
| 88 | config SB800_AHCI_ROM |
| 89 | bool "Add a AHCI ROM" |
| 90 | |
| 91 | config AHCI_ROM_FILE |
| 92 | string "AHCI ROM path and filename" |
| 93 | depends on SB800_AHCI_ROM |
| 94 | default "site-local/sb800/ahci.bin" |
| 95 | endif |
| 96 | |
| 97 | if SB800_SATA_RAID |
| 98 | config RAID_ROM_ID |
| 99 | string "RAID device PCI IDs" |
| 100 | default "1002,4393" |
| 101 | help |
| 102 | 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode |
| 103 | |
| 104 | config RAID_ROM_FILE |
| 105 | string "RAID ROM path and filename" |
| 106 | depends on SB800_SATA_RAID |
| 107 | default "site-local/sb800/raid.bin" |
| 108 | |
| 109 | config RAID_MISC_ROM_FILE |
| 110 | string "RAID Misc ROM path and filename" |
| 111 | default "site-local/sb800/misc.bin" |
| 112 | depends on SB800_SATA_RAID |
| 113 | |
Kerry Sheh | 55437c5 | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 114 | config RAID_MISC_ROM_POSITION |
| 115 | hex "RAID Misc ROM Position" |
| 116 | default 0xFFF00000 |
| 117 | depends on SB800_SATA_RAID |
| 118 | help |
| 119 | The RAID ROM requires that the MISC ROM is located between the range |
| 120 | 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. |
| 121 | The CONFIG_ROM_SIZE must larger than 0x100000. |
| 122 | |
Kerry Sheh | d4a0e7d | 2011-10-10 17:17:39 +0800 | [diff] [blame] | 123 | endif |
| 124 | |
Zheng Bao | f57d0dc | 2013-02-17 17:01:34 +0800 | [diff] [blame] | 125 | config S3_DATA_POS |
Zheng Bao | eb1d39b | 2012-08-27 17:45:01 +0800 | [diff] [blame] | 126 | hex "S3 volatile storage position" |
| 127 | default 0xFFFF0000 |
| 128 | depends on HAVE_ACPI_RESUME |
| 129 | help |
| 130 | For a system with S3 feature, the BIOS needs to save some data to |
Zheng Bao | 178df11 | 2013-02-17 16:41:14 +0800 | [diff] [blame] | 131 | non-volatile storage at cold boot stage. |
Zheng Bao | eb1d39b | 2012-08-27 17:45:01 +0800 | [diff] [blame] | 132 | |
Zheng Bao | 22ec9f9 | 2013-02-18 16:56:09 +0800 | [diff] [blame] | 133 | config S3_DATA_SIZE |
| 134 | int "S3 volatile storage size" |
| 135 | default 32768 |
| 136 | depends on HAVE_ACPI_RESUME |
| 137 | help |
| 138 | For a system with S3 feature, the BIOS needs to save some data to |
| 139 | non-volatile storage at cold boot stage. |
| 140 | |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 141 | config SB800_IMC_FWM |
| 142 | bool "Add IMC firmware" |
| 143 | default n |
| 144 | help |
| 145 | Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control. |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 146 | |
| 147 | if SB800_IMC_FWM |
| 148 | |
| 149 | config SB800_IMC_FWM_FILE |
| 150 | string "IMC firmware path and filename" |
| 151 | default "3rdparty/southbridge/amd/sb800/imc.bin" |
| 152 | |
| 153 | choice |
| 154 | prompt "SB800 Firmware ROM Position" |
| 155 | |
| 156 | config SB800_FWM_AT_FFFA0000 |
| 157 | bool "0xFFFA0000" |
| 158 | help |
| 159 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 160 | fixed locations in memory. The location used shouldn't matter, just |
| 161 | select an area that doesn't conflict with anything else. |
| 162 | |
| 163 | config SB800_FWM_AT_FFF20000 |
| 164 | bool "0xFFF20000" |
| 165 | help |
| 166 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 167 | fixed locations in memory. The location used shouldn't matter, just |
| 168 | select an area that doesn't conflict with anything else. |
| 169 | |
| 170 | config SB800_FWM_AT_FFE20000 |
| 171 | depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 || BOARD_ROMSIZE_KB_2048 |
| 172 | bool "0xFFE20000" |
| 173 | help |
| 174 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 175 | fixed locations in memory. The location used shouldn't matter, just |
| 176 | select an area that doesn't conflict with anything else. |
| 177 | |
| 178 | config SB800_FWM_AT_FFC20000 |
| 179 | depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 |
| 180 | bool "0xFFC20000" |
| 181 | help |
| 182 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 183 | fixed locations in memory. The location used shouldn't matter, just |
| 184 | select an area that doesn't conflict with anything else. |
| 185 | |
| 186 | config SB800_FWM_AT_FF820000 |
| 187 | depends on BOARD_ROMSIZE_KB_8192 |
| 188 | bool "0xFF820000" |
| 189 | help |
| 190 | The IMC and GEC ROMs requires a 'signature' located at one of several |
| 191 | fixed locations in memory. The location used shouldn't matter, just |
| 192 | select an area that doesn't conflict with anything else. |
| 193 | |
| 194 | endchoice |
| 195 | |
| 196 | config SB800_FWM_POSITION |
| 197 | hex |
| 198 | default 0xFFFA0000 if SB800_FWM_AT_FFFA0000 |
| 199 | default 0xFFF20000 if SB800_FWM_AT_FFF20000 |
| 200 | default 0xFFE20000 if SB800_FWM_AT_FFE20000 |
| 201 | default 0xFFC20000 if SB800_FWM_AT_FFC20000 |
Martin Roth | 238780c | 2013-01-08 13:46:50 -0700 | [diff] [blame] | 202 | default 0xFF820000 if SB800_FWM_AT_FF820000 |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 203 | |
| 204 | endif #SB800_IMC_FWM |
| 205 | |
| 206 | choice |
| 207 | prompt "Fan Control" |
| 208 | default SB800_NO_FAN_CONTROL |
| 209 | help |
| 210 | Select the method of SB800 fan control to be used. None would be |
| 211 | for either fixed maximum speed fans connected to the SB800 or for |
| 212 | an external chip controlling the fan speeds. Manual control sets |
| 213 | up the SB800 fan control registers. IMC fan control uses the SB800 |
| 214 | IMC to actively control the fan speeds. |
| 215 | |
| 216 | config SB800_NO_FAN_CONTROL |
| 217 | bool "None" |
| 218 | help |
| 219 | No SB800 Fan control - Do not set up the SB800 fan control registers. |
| 220 | |
| 221 | config SB800_MANUAL_FAN_CONTROL |
| 222 | bool "Manual" |
| 223 | help |
| 224 | Configure the SB800 fan control registers in devicetree.cb. |
| 225 | |
| 226 | config SB800_IMC_FAN_CONTROL |
| 227 | bool "IMC Based" |
| 228 | depends on SB800_IMC_FWM |
| 229 | help |
| 230 | Set up the SB800 to use the IMC based Fan controller. This requires |
| 231 | the IMC rom from AMD. Configure the registers in devicetree.cb. |
| 232 | |
| 233 | endchoice |
| 234 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 235 | endif #SOUTHBRIDGE_AMD_CIMX_SB800 |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 236 | |