Martin Roth | 7d86f34 | 2024-02-16 11:04:02 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Felix Held | d123f8d | 2023-12-15 10:57:30 +0100 | [diff] [blame] | 3 | config SOC_AMD_GENOA_POC |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 4 | bool |
| 5 | |
Felix Held | d123f8d | 2023-12-15 10:57:30 +0100 | [diff] [blame] | 6 | if SOC_AMD_GENOA_POC |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 7 | |
| 8 | config SOC_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Felix Held | d1065a3 | 2023-12-12 19:36:55 +0100 | [diff] [blame] | 10 | select ACPI_SOC_NVS |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 11 | select ARCH_X86 |
Varshit Pandya | 0f666f7 | 2023-12-18 23:07:21 +0530 | [diff] [blame] | 12 | select DEFAULT_X2APIC |
Felix Held | d1065a3 | 2023-12-12 19:36:55 +0100 | [diff] [blame] | 13 | select HAVE_ACPI_TABLES |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 14 | select HAVE_EXP_X86_64_SUPPORT |
Arthur Heymans | 2e2f166 | 2023-07-14 22:58:49 +0200 | [diff] [blame] | 15 | select HAVE_SMI_HANDLER |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 16 | select RESET_VECTOR_IN_RAM |
| 17 | select SOC_AMD_COMMON |
Arthur Heymans | 2e2f166 | 2023-07-14 22:58:49 +0200 | [diff] [blame] | 18 | select SOC_AMD_COMMON_BLOCK_ACPI |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 19 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | d1065a3 | 2023-12-12 19:36:55 +0100 | [diff] [blame] | 20 | select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE |
Felix Held | b499c1f | 2023-12-12 20:39:38 +0100 | [diff] [blame] | 21 | select SOC_AMD_COMMON_BLOCK_ACPI_IVRS |
Felix Held | aab8a22 | 2024-01-08 23:30:38 +0100 | [diff] [blame] | 22 | select SOC_AMD_COMMON_BLOCK_ACPI_MADT |
Arthur Heymans | 4da9d6b4 | 2023-07-13 14:19:09 +0200 | [diff] [blame] | 23 | select SOC_AMD_COMMON_BLOCK_AOAC |
Varshit Pandya | 95d78d9 | 2023-10-04 19:30:21 +0530 | [diff] [blame] | 24 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Arthur Heymans | 48167b1 | 2023-07-13 14:07:54 +0200 | [diff] [blame] | 25 | select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 26 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
| 27 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN |
| 28 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT |
| 29 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO |
Arthur Heymans | c666a91 | 2023-07-13 14:34:10 +0200 | [diff] [blame] | 30 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Felix Held | d26f5a1 | 2023-11-20 16:31:31 +0100 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_I2C |
Arthur Heymans | c5122f9 | 2023-07-14 23:27:31 +0200 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_IOMMU |
Arthur Heymans | c666a91 | 2023-07-13 14:34:10 +0200 | [diff] [blame] | 33 | select SOC_AMD_COMMON_BLOCK_LPC |
Arthur Heymans | 447e279 | 2023-07-14 23:05:46 +0200 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_MCAX |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_NONCAR |
Felix Held | 80434a6 | 2023-12-13 23:11:45 +0100 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_PCI |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Felix Held | 0f209b5 | 2023-10-26 14:27:57 +0200 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Felix Held | 51d1f30 | 2023-10-04 21:10:36 +0200 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_PSP_SPL |
Varshit Pandya | c0f1983 | 2023-10-04 19:26:21 +0530 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_SMI |
Arthur Heymans | 2e2f166 | 2023-07-14 22:58:49 +0200 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_SMM |
Varshit Pandya | 0a2d2a9 | 2023-10-16 17:26:35 +0530 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_SMU |
| 43 | select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY |
Felix Held | d1065a3 | 2023-12-12 19:36:55 +0100 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_SVI3 |
Arthur Heymans | 48167b1 | 2023-07-13 14:07:54 +0200 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_TSC |
Varshit Pandya | 970d770 | 2023-10-06 18:14:02 +0530 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_UART |
Arthur Heymans | 5ee1d23 | 2023-07-14 23:16:22 +0200 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_UCODE |
Arthur Heymans | c666a91 | 2023-07-13 14:34:10 +0200 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_USE_ESPI |
Martin Roth | 50a3d6f | 2023-10-25 16:17:16 -0600 | [diff] [blame] | 49 | select SOC_AMD_OPENSIL |
Felix Held | 9314bb6 | 2023-12-15 11:15:26 +0100 | [diff] [blame] | 50 | select SOC_AMD_OPENSIL_GENOA_POC |
Arthur Heymans | e4eba13 | 2023-07-13 14:02:42 +0200 | [diff] [blame] | 51 | select X86_CUSTOM_BOOTMEDIA |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 52 | |
| 53 | config USE_EXP_X86_64_SUPPORT |
| 54 | default y |
| 55 | |
vbpandya | 87d8b8c | 2023-09-22 20:49:37 +0530 | [diff] [blame] | 56 | config CHIPSET_DEVICETREE |
| 57 | string |
Felix Held | d123f8d | 2023-12-15 10:57:30 +0100 | [diff] [blame] | 58 | default "soc/amd/genoa_poc/chipset.cb" |
vbpandya | 87d8b8c | 2023-09-22 20:49:37 +0530 | [diff] [blame] | 59 | |
Felix Held | d26f5a1 | 2023-11-20 16:31:31 +0100 | [diff] [blame] | 60 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 61 | int |
| 62 | default 150 |
| 63 | |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 64 | config EARLY_RESERVED_DRAM_BASE |
| 65 | hex |
| 66 | default 0x7000000 |
| 67 | help |
| 68 | This variable defines the base address of the DRAM which is reserved |
| 69 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 70 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 71 | not use it, thus preventing corruption of OS memory in case of S3 |
| 72 | resume. |
| 73 | |
| 74 | config EARLYRAM_BSP_STACK_SIZE |
| 75 | hex |
| 76 | default 0x1000 |
| 77 | |
Varshit Pandya | a775958 | 2023-10-17 21:59:39 +0530 | [diff] [blame] | 78 | config MAX_CPUS |
| 79 | int |
| 80 | default 384 |
| 81 | |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 82 | config PSP_APOB_DRAM_ADDRESS |
| 83 | hex |
| 84 | default 0x7001000 |
| 85 | help |
| 86 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 87 | Block. |
| 88 | |
| 89 | config PSP_APOB_DRAM_SIZE |
| 90 | hex |
| 91 | default 0x20000 |
| 92 | |
| 93 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 94 | hex |
| 95 | default 0x1600 |
| 96 | help |
| 97 | Increase this value if preram cbmem console is getting truncated |
| 98 | |
| 99 | config C_ENV_BOOTBLOCK_SIZE |
| 100 | hex |
| 101 | default 0x10000 |
| 102 | help |
| 103 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 104 | This variable controls the DRAM allocation size in linker script |
| 105 | for bootblock stage. |
| 106 | |
| 107 | config ROMSTAGE_ADDR |
| 108 | hex |
| 109 | default 0x7040000 |
| 110 | help |
| 111 | Sets the address in DRAM where romstage should be loaded. |
| 112 | |
| 113 | config ROMSTAGE_SIZE |
| 114 | hex |
| 115 | default 0x80000 |
| 116 | help |
| 117 | Sets the size of DRAM allocation for romstage in linker script. |
| 118 | |
Arthur Heymans | 901f040 | 2023-07-13 14:14:55 +0200 | [diff] [blame] | 119 | config ECAM_MMCONF_BASE_ADDRESS |
| 120 | hex |
| 121 | default 0xE0000000 |
| 122 | |
| 123 | config ECAM_MMCONF_BUS_NUMBER |
| 124 | int |
| 125 | default 256 |
| 126 | |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 127 | menu "PSP Configuration Options" |
| 128 | |
| 129 | config AMDFW_CONFIG_FILE |
| 130 | string |
Felix Held | d123f8d | 2023-12-15 10:57:30 +0100 | [diff] [blame] | 131 | default "src/soc/amd/genoa_poc/fw.cfg" |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 132 | |
| 133 | config PSP_DISABLE_POSTCODES |
| 134 | bool "Disable PSP post codes" |
| 135 | help |
| 136 | Disables the output of port80 post codes from PSP. |
| 137 | |
| 138 | config PSP_INIT_ESPI |
| 139 | bool "Initialize eSPI in PSP Stage 2 Boot Loader" |
| 140 | help |
| 141 | Select to initialize the eSPI controller in the PSP Stage 2 Boot |
| 142 | Loader. |
| 143 | |
| 144 | config PSP_UNLOCK_SECURE_DEBUG |
| 145 | bool |
| 146 | default y |
| 147 | |
| 148 | config HAVE_PSP_WHITELIST_FILE |
| 149 | bool "Include a debug whitelist file in PSP build" |
| 150 | default n |
| 151 | help |
| 152 | Support secured unlock prior to reset using a whitelisted |
| 153 | serial number. This feature requires a signed whitelist image |
| 154 | and bootloader from AMD. |
| 155 | |
| 156 | If unsure, answer 'n' |
| 157 | |
| 158 | config PSP_WHITELIST_FILE |
| 159 | string "Debug whitelist file path" |
| 160 | depends on HAVE_PSP_WHITELIST_FILE |
| 161 | |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 162 | config PSP_SOFTFUSE_BITS |
| 163 | string "PSP Soft Fuse bits to enable" |
| 164 | default "" |
| 165 | help |
| 166 | Space separated list of Soft Fuse bits to enable. |
| 167 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 168 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 169 | (Set by PSP_DISABLE_PORT80) |
| 170 | Bit 15: PSP debug output destination: |
| 171 | 0=SoC MMIO UART, 1=IO port 0x3F8 |
| 172 | |
| 173 | See #57299 (NDA) for additional bit definitions. |
| 174 | endmenu |
| 175 | |
Felix Held | 88da16b | 2023-12-04 18:46:38 +0100 | [diff] [blame] | 176 | config CONSOLE_UART_BASE_ADDRESS |
| 177 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 178 | hex |
| 179 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 180 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 181 | default 0xfedce000 if UART_FOR_CONSOLE = 2 |
| 182 | |
Arthur Heymans | 2e2f166 | 2023-07-14 22:58:49 +0200 | [diff] [blame] | 183 | config SMM_TSEG_SIZE |
| 184 | hex |
| 185 | default 0x800000 |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 186 | |
Felix Held | d1065a3 | 2023-12-12 19:36:55 +0100 | [diff] [blame] | 187 | config ACPI_SSDT_PSD_INDEPENDENT |
| 188 | bool "Allow core p-state independent transitions" |
| 189 | default y |
| 190 | help |
| 191 | AMD recommends the ACPI _PSD object to be configured to cause |
| 192 | cores to transition between p-states independently. A vendor may |
| 193 | choose to generate _PSD object to allow cores to transition together. |
| 194 | |
Arthur Heymans | b2ea2f2 | 2023-07-15 00:28:31 +0200 | [diff] [blame] | 195 | config ACPI_BERT |
| 196 | bool "Build ACPI BERT Table" |
| 197 | default y |
| 198 | depends on HAVE_ACPI_TABLES |
| 199 | help |
| 200 | Report Machine Check errors identified in POST to the OS in an |
| 201 | ACPI Boot Error Record Table. |
| 202 | |
| 203 | config ACPI_BERT_SIZE |
| 204 | hex |
| 205 | default 0x4000 if ACPI_BERT |
| 206 | default 0x0 |
| 207 | help |
| 208 | Specify the amount of DRAM reserved for gathering the data used to |
| 209 | generate the ACPI table. |
| 210 | |
Felix Held | d123f8d | 2023-12-15 10:57:30 +0100 | [diff] [blame] | 211 | endif # SOC_AMD_GENOA_POC |