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Aaron Durbin3d0071b2013-01-18 14:32:50 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 ChromeOS Authors
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <stdint.h>
Aaron Durbin7492ec12013-02-08 22:18:04 -060021#include <string.h>
Aaron Durbin3d0071b2013-01-18 14:32:50 -060022#include <cbmem.h>
23#include <console/console.h>
Aaron Durbina2671612013-02-06 21:41:01 -060024#include <arch/cpu.h>
25#include <cpu/x86/bist.h>
26#include <cpu/x86/msr.h>
Aaron Durbin38d94232013-02-07 00:03:33 -060027#include <cpu/x86/mtrr.h>
Patrick Georgibd79c5e2014-11-28 22:35:36 +010028#include <halt.h>
Aaron Durbina2671612013-02-06 21:41:01 -060029#include <lib.h>
30#include <timestamp.h>
31#include <arch/io.h>
Aaron Durbin7492ec12013-02-08 22:18:04 -060032#include <arch/stages.h>
Aaron Durbina2671612013-02-06 21:41:01 -060033#include <device/pci_def.h>
34#include <cpu/x86/lapic.h>
Aaron Durbinf7cdfe52013-02-16 00:05:52 -060035#include <cbfs.h>
Aaron Durbin75e29742013-10-10 20:37:04 -050036#include <ramstage_cache.h>
Aaron Durbinbf396ff2013-02-11 21:50:35 -060037#include <romstage_handoff.h>
Aaron Durbinb86113f2013-02-19 08:59:16 -060038#include <reset.h>
Aaron Durbina2671612013-02-06 21:41:01 -060039#include <vendorcode/google/chromeos/chromeos.h>
Duncan Laurie7cced0d2013-06-04 10:03:34 -070040#if CONFIG_EC_GOOGLE_CHROMEEC
41#include <ec/google/chromeec/ec.h>
42#endif
Aaron Durbina2671612013-02-06 21:41:01 -060043#include "haswell.h"
44#include "northbridge/intel/haswell/haswell.h"
45#include "northbridge/intel/haswell/raminit.h"
46#include "southbridge/intel/lynxpoint/pch.h"
47#include "southbridge/intel/lynxpoint/me.h"
Aaron Durbin3d0071b2013-01-18 14:32:50 -060048
Aaron Durbina2671612013-02-06 21:41:01 -060049
Aaron Durbinb86113f2013-02-19 08:59:16 -060050static inline void reset_system(void)
51{
52 hard_reset();
Patrick Georgibd79c5e2014-11-28 22:35:36 +010053 halt();
Aaron Durbinb86113f2013-02-19 08:59:16 -060054}
55
Aaron Durbin38d94232013-02-07 00:03:33 -060056/* The cache-as-ram assembly file calls romstage_main() after setting up
57 * cache-as-ram. romstage_main() will then call the mainboards's
58 * mainboard_romstage_entry() function. That function then calls
59 * romstage_common() below. The reason for the back and forth is to provide
60 * common entry point from cache-as-ram while still allowing for code sharing.
61 * Because we can't use global variables the stack is used for allocations --
62 * thus the need to call back and forth. */
Aaron Durbin3d0071b2013-01-18 14:32:50 -060063
Aaron Durbin38d94232013-02-07 00:03:33 -060064
65static inline u32 *stack_push(u32 *stack, u32 value)
66{
67 stack = &stack[-1];
68 *stack = value;
69 return stack;
70}
71
Aaron Durbinc0cbd6e2013-03-13 13:51:20 -050072/* Romstage needs quite a bit of stack for decompressing images since the lzma
73 * lib keeps its state on the stack during romstage. */
74#define ROMSTAGE_RAM_STACK_SIZE 0x5000
Aaron Durbine2d9e5b2013-02-08 17:38:35 -060075static unsigned long choose_top_of_stack(void)
76{
77 unsigned long stack_top;
Aaron Durbinc0cbd6e2013-03-13 13:51:20 -050078#if CONFIG_DYNAMIC_CBMEM
79 /* cbmem_add() does a find() before add(). */
80 stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
81 ROMSTAGE_RAM_STACK_SIZE);
82 stack_top += ROMSTAGE_RAM_STACK_SIZE;
Aaron Durbine2d9e5b2013-02-08 17:38:35 -060083#else
Kyösti Mälkki1729cd82014-10-16 12:47:25 +030084 stack_top = CONFIG_RAMTOP;
Aaron Durbine2d9e5b2013-02-08 17:38:35 -060085#endif
86 return stack_top;
87}
88
Aaron Durbin38d94232013-02-07 00:03:33 -060089/* setup_romstage_stack_after_car() determines the stack to use after
90 * cache-as-ram is torn down as well as the MTRR settings to use. */
91static void *setup_romstage_stack_after_car(void)
92{
93 unsigned long top_of_stack;
94 int num_mtrrs;
95 u32 *slot;
96 u32 mtrr_mask_upper;
Aaron Durbin67481ddc2013-02-15 15:08:37 -060097 u32 top_of_ram;
Aaron Durbin38d94232013-02-07 00:03:33 -060098
99 /* Top of stack needs to be aligned to a 4-byte boundary. */
Aaron Durbine2d9e5b2013-02-08 17:38:35 -0600100 top_of_stack = choose_top_of_stack() & ~3;
Aaron Durbin38d94232013-02-07 00:03:33 -0600101 slot = (void *)top_of_stack;
102 num_mtrrs = 0;
103
104 /* The upper bits of the MTRR mask need to set according to the number
105 * of physical address bits. */
106 mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
107
Paul Menzel4fe98132014-01-25 15:55:28 +0100108 /* The order for each MTRR is value then base with upper 32-bits of
Aaron Durbin38d94232013-02-07 00:03:33 -0600109 * each value coming before the lower 32-bits. The reasoning for
110 * this ordering is to create a stack layout like the following:
111 * +0: Number of MTRRs
Paul Menzel4fe98132014-01-25 15:55:28 +0100112 * +4: MTRR base 0 31:0
113 * +8: MTRR base 0 63:32
114 * +12: MTRR mask 0 31:0
115 * +16: MTRR mask 0 63:32
116 * +20: MTRR base 1 31:0
117 * +24: MTRR base 1 63:32
118 * +28: MTRR mask 1 31:0
119 * +32: MTRR mask 1 63:32
Aaron Durbin38d94232013-02-07 00:03:33 -0600120 */
121
122 /* Cache the ROM as WP just below 4GiB. */
123 slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200124 slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid);
Aaron Durbin38d94232013-02-07 00:03:33 -0600125 slot = stack_push(slot, 0); /* upper base */
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200126 slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
Aaron Durbin38d94232013-02-07 00:03:33 -0600127 num_mtrrs++;
128
129 /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
130 slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
131 slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid);
132 slot = stack_push(slot, 0); /* upper base */
133 slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
134 num_mtrrs++;
135
Aaron Durbin67481ddc2013-02-15 15:08:37 -0600136 top_of_ram = get_top_of_ram();
Aaron Durbin38d94232013-02-07 00:03:33 -0600137 /* Cache 8MiB below the top of ram. On haswell systems the top of
138 * ram under 4GiB is the start of the TSEG region. It is required to
139 * be 8MiB aligned. Set this area as cacheable so it can be used later
140 * for ramstage before setting up the entire RAM as cacheable. */
141 slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
142 slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
143 slot = stack_push(slot, 0); /* upper base */
Aaron Durbin67481ddc2013-02-15 15:08:37 -0600144 slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
145 num_mtrrs++;
146
147 /* Cache 8MiB at the top of ram. Top of ram on haswell systems
148 * is where the TSEG region resides. However, it is not restricted
149 * to SMM mode until SMM has been relocated. By setting the region
150 * to cacheable it provides faster access when relocating the SMM
151 * handler as well as using the TSEG region for other purposes. */
152 slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
153 slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
154 slot = stack_push(slot, 0); /* upper base */
155 slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
Aaron Durbin38d94232013-02-07 00:03:33 -0600156 num_mtrrs++;
157
Paul Menzel4fe98132014-01-25 15:55:28 +0100158 /* Save the number of MTRRs to setup. Return the stack location
Aaron Durbin38d94232013-02-07 00:03:33 -0600159 * pointing to the number of MTRRs. */
160 slot = stack_push(slot, num_mtrrs);
161
162 return slot;
163}
164
Aaron Durbin39ecc652013-05-02 09:42:13 -0500165void * asmlinkage romstage_main(unsigned long bist)
Aaron Durbin3d0071b2013-01-18 14:32:50 -0600166{
167 int i;
Aaron Durbin38d94232013-02-07 00:03:33 -0600168 void *romstage_stack_after_car;
Aaron Durbin3d0071b2013-01-18 14:32:50 -0600169 const int num_guards = 4;
170 const u32 stack_guard = 0xdeadbeef;
171 u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
172 CONFIG_DCACHE_RAM_SIZE -
173 CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
174
175 printk(BIOS_DEBUG, "Setting up stack guards.\n");
176 for (i = 0; i < num_guards; i++)
177 stack_base[i] = stack_guard;
178
Aaron Durbina2671612013-02-06 21:41:01 -0600179 mainboard_romstage_entry(bist);
Aaron Durbin3d0071b2013-01-18 14:32:50 -0600180
181 /* Check the stack. */
182 for (i = 0; i < num_guards; i++) {
183 if (stack_base[i] == stack_guard)
184 continue;
185 printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
186 }
187
Aaron Durbin38d94232013-02-07 00:03:33 -0600188 /* Get the stack to use after cache-as-ram is torn down. */
189 romstage_stack_after_car = setup_romstage_stack_after_car();
190
Aaron Durbin38d94232013-02-07 00:03:33 -0600191 return romstage_stack_after_car;
Aaron Durbin3d0071b2013-01-18 14:32:50 -0600192}
Aaron Durbina2671612013-02-06 21:41:01 -0600193
194void romstage_common(const struct romstage_params *params)
195{
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600196 int boot_mode;
Aaron Durbina2671612013-02-06 21:41:01 -0600197 int wake_from_s3;
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600198 struct romstage_handoff *handoff;
Aaron Durbina2671612013-02-06 21:41:01 -0600199
Kyösti Mälkki3d45c402013-09-07 20:26:36 +0300200 timestamp_init(get_initial_timestamp());
201 timestamp_add_now(TS_START_ROMSTAGE);
Aaron Durbina2671612013-02-06 21:41:01 -0600202
203 if (params->bist == 0)
204 enable_lapic();
205
206 wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
207
Duncan Laurie7cced0d2013-06-04 10:03:34 -0700208#if CONFIG_EC_GOOGLE_CHROMEEC
209 /* Ensure the EC is in the right mode for recovery */
210 google_chromeec_early_init();
211#endif
212
Aaron Durbina2671612013-02-06 21:41:01 -0600213 /* Halt if there was a built in self test failure */
214 report_bist_failure(params->bist);
215
216 /* Perform some early chipset initialization required
217 * before RAM initialization can work
218 */
219 haswell_early_initialization(HASWELL_MOBILE);
220 printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
221
222 if (wake_from_s3) {
223#if CONFIG_HAVE_ACPI_RESUME
224 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
Aaron Durbina2671612013-02-06 21:41:01 -0600225#else
226 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600227 wake_from_s3 = 0;
Aaron Durbina2671612013-02-06 21:41:01 -0600228#endif
229 }
230
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600231 /* There are hard coded assumptions of 2 meaning s3 wake. Normalize
232 * the users of the 2 literal here based off wake_from_s3. */
233 boot_mode = wake_from_s3 ? 2 : 0;
234
Aaron Durbina2671612013-02-06 21:41:01 -0600235 /* Prepare USB controller early in S3 resume */
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600236 if (wake_from_s3)
Aaron Durbina2671612013-02-06 21:41:01 -0600237 enable_usb_bar();
238
239 post_code(0x3a);
240 params->pei_data->boot_mode = boot_mode;
Kyösti Mälkki3d45c402013-09-07 20:26:36 +0300241
242 timestamp_add_now(TS_BEFORE_INITRAM);
Aaron Durbina2671612013-02-06 21:41:01 -0600243
244 report_platform_info();
245
Aaron Durbinc7633f42013-06-13 17:29:36 -0700246 if (params->copy_spd != NULL)
247 params->copy_spd(params->pei_data);
248
Aaron Durbina2671612013-02-06 21:41:01 -0600249 sdram_initialize(params->pei_data);
250
Kyösti Mälkki3d45c402013-09-07 20:26:36 +0300251 timestamp_add_now(TS_AFTER_INITRAM);
252
Aaron Durbina2671612013-02-06 21:41:01 -0600253 post_code(0x3b);
254
255 intel_early_me_status();
256
257 quick_ram_check();
258 post_code(0x3e);
259
Aaron Durbinc0cbd6e2013-03-13 13:51:20 -0500260 if (!wake_from_s3) {
261 cbmem_initialize_empty();
262 /* Save data returned from MRC on non-S3 resumes. */
Aaron Durbin2ad1dba2013-02-07 00:51:18 -0600263 save_mrc_data(params->pei_data);
Aaron Durbinc0cbd6e2013-03-13 13:51:20 -0500264 } else if (cbmem_initialize()) {
265 #if CONFIG_HAVE_ACPI_RESUME
Aaron Durbina2671612013-02-06 21:41:01 -0600266 /* Failed S3 resume, reset to come up cleanly */
Aaron Durbinb86113f2013-02-19 08:59:16 -0600267 reset_system();
Aaron Durbinc0cbd6e2013-03-13 13:51:20 -0500268 #endif
Aaron Durbina2671612013-02-06 21:41:01 -0600269 }
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600270
271 handoff = romstage_handoff_find_or_add();
272 if (handoff != NULL)
273 handoff->s3_resume = wake_from_s3;
274 else
275 printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
276
Aaron Durbina2671612013-02-06 21:41:01 -0600277 post_code(0x3f);
278#if CONFIG_CHROMEOS
279 init_chromeos(boot_mode);
280#endif
Aaron Durbina2671612013-02-06 21:41:01 -0600281 timestamp_add_now(TS_END_ROMSTAGE);
Aaron Durbina2671612013-02-06 21:41:01 -0600282}
Aaron Durbin7492ec12013-02-08 22:18:04 -0600283
Aaron Durbind02bb622013-03-01 17:40:49 -0600284static inline void prepare_for_resume(struct romstage_handoff *handoff)
Aaron Durbin7492ec12013-02-08 22:18:04 -0600285{
Aaron Durbine2d9e5b2013-02-08 17:38:35 -0600286/* Only need to save memory when ramstage isn't relocatable. */
287#if !CONFIG_RELOCATABLE_RAMSTAGE
Aaron Durbin7492ec12013-02-08 22:18:04 -0600288#if CONFIG_HAVE_ACPI_RESUME
289 /* Back up the OS-controlled memory where ramstage will be loaded. */
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600290 if (handoff != NULL && handoff->s3_resume) {
Aaron Durbin7492ec12013-02-08 22:18:04 -0600291 void *src = (void *)CONFIG_RAMBASE;
Aaron Durbinbf396ff2013-02-11 21:50:35 -0600292 void *dest = cbmem_find(CBMEM_ID_RESUME);
293 if (dest != NULL)
294 memcpy(dest, src, HIGH_MEMORY_SAVE);
Aaron Durbin7492ec12013-02-08 22:18:04 -0600295 }
296#endif
Aaron Durbine2d9e5b2013-02-08 17:38:35 -0600297#endif
Aaron Durbin7492ec12013-02-08 22:18:04 -0600298}
299
300void romstage_after_car(void)
301{
Aaron Durbind02bb622013-03-01 17:40:49 -0600302 struct romstage_handoff *handoff;
303
304 handoff = romstage_handoff_find_or_add();
305
306 prepare_for_resume(handoff);
307
Aaron Durbin7492ec12013-02-08 22:18:04 -0600308 /* Load the ramstage. */
Stefan Reinauer648d1662013-05-06 18:05:39 -0700309 copy_and_run();
Aaron Durbin7492ec12013-02-08 22:18:04 -0600310}
Aaron Durbinf7cdfe52013-02-16 00:05:52 -0600311
312
313#if CONFIG_RELOCATABLE_RAMSTAGE
Aaron Durbin75e29742013-10-10 20:37:04 -0500314#include <ramstage_cache.h>
315
316struct ramstage_cache *ramstage_cache_location(long *size)
Aaron Durbinf7cdfe52013-02-16 00:05:52 -0600317{
Aaron Durbinf7cdfe52013-02-16 00:05:52 -0600318 /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
319 * The top of ram is defined to be the TSEG base address. */
Aaron Durbin75e29742013-10-10 20:37:04 -0500320 *size = RESERVED_SMM_SIZE;
321 return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
Aaron Durbinf7cdfe52013-02-16 00:05:52 -0600322}
323
Aaron Durbin75e29742013-10-10 20:37:04 -0500324void ramstage_cache_invalid(struct ramstage_cache *cache)
Aaron Durbinf7cdfe52013-02-16 00:05:52 -0600325{
Aaron Durbin75e29742013-10-10 20:37:04 -0500326#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
327 reset_system();
328#endif
Aaron Durbinf7cdfe52013-02-16 00:05:52 -0600329}
330#endif