Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
| 9 | #include <delay.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 10 | #include <soc/rcba.h> |
| 11 | #include <soc/sata.h> |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 12 | #include <soc/intel/broadwell/pch/chip.h> |
Angel Pons | c423ce2 | 2021-04-19 16:13:31 +0200 | [diff] [blame] | 13 | #include <southbridge/intel/lynxpoint/iobp.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | |
| 15 | static inline u32 sir_read(struct device *dev, int idx) |
| 16 | { |
| 17 | pci_write_config32(dev, SATA_SIRI, idx); |
| 18 | return pci_read_config32(dev, SATA_SIRD); |
| 19 | } |
| 20 | |
| 21 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 22 | { |
| 23 | pci_write_config32(dev, SATA_SIRI, idx); |
| 24 | pci_write_config32(dev, SATA_SIRD, value); |
| 25 | } |
| 26 | |
| 27 | static void sata_init(struct device *dev) |
| 28 | { |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 29 | const struct soc_intel_broadwell_pch_config *config = config_of(dev); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 30 | u32 reg32; |
| 31 | u8 *abar; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 32 | u16 reg16; |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 33 | int port; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 34 | |
| 35 | printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); |
| 36 | |
Angel Pons | 11fdb17 | 2020-10-30 14:18:40 +0100 | [diff] [blame] | 37 | /* Enable memory space decoding for ABAR */ |
| 38 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 39 | |
| 40 | /* Set Interrupt Line */ |
| 41 | /* Interrupt Pin is set by D31IP.PIP */ |
| 42 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); |
| 43 | |
| 44 | /* Set timings */ |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 45 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); |
| 46 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 47 | |
| 48 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 49 | reg16 = pci_read_config16(dev, 0x92); |
Wenkai Du | 038cce2 | 2014-12-05 14:04:10 -0800 | [diff] [blame] | 50 | reg16 &= ~0xf; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 51 | reg16 |= 0x8000 | config->sata_port_map; |
| 52 | pci_write_config16(dev, 0x92, reg16); |
| 53 | udelay(2); |
| 54 | |
| 55 | /* Setup register 98h */ |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 56 | reg32 = pci_read_config32(dev, 0x98); |
Angel Pons | 316d687 | 2020-10-30 16:01:05 +0100 | [diff] [blame^] | 57 | reg32 |= 1 << 19; |
| 58 | reg32 |= 1 << 22; |
| 59 | reg32 &= ~(0x3f << 7); |
| 60 | reg32 |= 0x04 << 7; |
| 61 | reg32 |= 1 << 20; |
| 62 | reg32 &= ~(0x03 << 5); |
| 63 | reg32 |= 1 << 5; |
| 64 | reg32 |= 1 << 18; |
| 65 | reg32 |= 1 << 29; /* Enable clock gating */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 66 | reg32 &= ~((1 << 31) | (1 << 30)); |
| 67 | reg32 |= 1 << 23; |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 68 | reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 69 | pci_write_config32(dev, 0x98, reg32); |
| 70 | |
| 71 | /* Setup register 9Ch */ |
Elyes HAOUAS | 878b685 | 2019-10-18 19:52:22 +0200 | [diff] [blame] | 72 | reg16 = (1 << 5); /* BWG step 12 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 73 | pci_write_config16(dev, 0x9c, reg16); |
| 74 | |
| 75 | /* SATA Initialization register */ |
| 76 | reg32 = 0x183; |
Wenkai Du | 038cce2 | 2014-12-05 14:04:10 -0800 | [diff] [blame] | 77 | reg32 |= (config->sata_port_map ^ 0xf) << 24; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 78 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 79 | pci_write_config32(dev, 0x94, reg32); |
| 80 | |
| 81 | /* Initialize AHCI memory-mapped space */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 82 | abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); |
| 83 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 84 | |
Duncan Laurie | 55228ba | 2014-08-25 10:14:08 -0700 | [diff] [blame] | 85 | /* CAP (HBA Capabilities) : enable power management */ |
| 86 | reg32 = read32(abar + 0x00); |
| 87 | reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ |
| 88 | reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ |
| 89 | reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ |
| 90 | write32(abar + 0x00, reg32); |
| 91 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 92 | /* PI (Ports implemented) */ |
| 93 | write32(abar + 0x0c, config->sata_port_map); |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 94 | (void)read32(abar + 0x0c); /* Read back 1 */ |
| 95 | (void)read32(abar + 0x0c); /* Read back 2 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 96 | |
| 97 | /* CAP2 (HBA Capabilities Extended)*/ |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 98 | if (config->sata_devslp_disable) { |
| 99 | reg32 = read32(abar + 0x24); |
| 100 | reg32 &= ~(1 << 3); |
| 101 | write32(abar + 0x24, reg32); |
| 102 | } else { |
| 103 | /* Enable DEVSLP */ |
| 104 | reg32 = read32(abar + 0x24); |
| 105 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 106 | write32(abar + 0x24, reg32); |
| 107 | |
| 108 | for (port = 0; port < 4; port++) { |
| 109 | if (!(config->sata_port_map & (1 << port))) |
| 110 | continue; |
| 111 | reg32 = read32(abar + 0x144 + (0x80 * port)); |
| 112 | reg32 |= (1 << 1); /* DEVSLP DSP */ |
| 113 | write32(abar + 0x144 + (0x80 * port), reg32); |
| 114 | } |
| 115 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 116 | |
| 117 | /* |
| 118 | * Static Power Gating for unused ports |
| 119 | */ |
| 120 | reg32 = RCBA32(0x3a84); |
| 121 | /* Port 3 and 2 disabled */ |
| 122 | if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) |
| 123 | reg32 |= (1 << 24) | (1 << 26); |
| 124 | /* Port 1 and 0 disabled */ |
| 125 | if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) |
| 126 | reg32 |= (1 << 20) | (1 << 18); |
| 127 | RCBA32(0x3a84) = reg32; |
| 128 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 129 | /* Set Gen3 Transmitter settings if needed */ |
| 130 | if (config->sata_port0_gen3_tx) |
Duncan Laurie | b63d341 | 2015-01-06 13:32:42 -0800 | [diff] [blame] | 131 | pch_iobp_update(SATA_IOBP_SP0_SECRT88, |
| 132 | ~(SATA_SECRT88_VADJ_MASK << |
| 133 | SATA_SECRT88_VADJ_SHIFT), |
| 134 | (config->sata_port0_gen3_tx & |
| 135 | SATA_SECRT88_VADJ_MASK) |
| 136 | << SATA_SECRT88_VADJ_SHIFT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 137 | |
| 138 | if (config->sata_port1_gen3_tx) |
Duncan Laurie | b63d341 | 2015-01-06 13:32:42 -0800 | [diff] [blame] | 139 | pch_iobp_update(SATA_IOBP_SP1_SECRT88, |
| 140 | ~(SATA_SECRT88_VADJ_MASK << |
| 141 | SATA_SECRT88_VADJ_SHIFT), |
| 142 | (config->sata_port1_gen3_tx & |
| 143 | SATA_SECRT88_VADJ_MASK) |
| 144 | << SATA_SECRT88_VADJ_SHIFT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 145 | |
Youness Alaoui | 696ebc2 | 2017-02-07 13:54:45 -0500 | [diff] [blame] | 146 | if (config->sata_port2_gen3_tx) |
| 147 | pch_iobp_update(SATA_IOBP_SP2_SECRT88, |
| 148 | ~(SATA_SECRT88_VADJ_MASK << |
| 149 | SATA_SECRT88_VADJ_SHIFT), |
| 150 | (config->sata_port2_gen3_tx & |
| 151 | SATA_SECRT88_VADJ_MASK) |
| 152 | << SATA_SECRT88_VADJ_SHIFT); |
| 153 | |
| 154 | if (config->sata_port3_gen3_tx) |
| 155 | pch_iobp_update(SATA_IOBP_SP3_SECRT88, |
| 156 | ~(SATA_SECRT88_VADJ_MASK << |
| 157 | SATA_SECRT88_VADJ_SHIFT), |
Youness Alaoui | 601aa31 | 2017-02-27 12:03:39 -0500 | [diff] [blame] | 158 | (config->sata_port3_gen3_tx & |
Youness Alaoui | 696ebc2 | 2017-02-07 13:54:45 -0500 | [diff] [blame] | 159 | SATA_SECRT88_VADJ_MASK) |
| 160 | << SATA_SECRT88_VADJ_SHIFT); |
| 161 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 162 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 163 | if (config->sata_port0_gen3_dtle) { |
| 164 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 165 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 166 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 167 | << SATA_DTLE_DATA_SHIFT); |
| 168 | |
| 169 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 170 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 171 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 172 | << SATA_DTLE_EDGE_SHIFT); |
| 173 | } |
| 174 | |
| 175 | if (config->sata_port1_gen3_dtle) { |
| 176 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 177 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 178 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 179 | << SATA_DTLE_DATA_SHIFT); |
| 180 | |
| 181 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 182 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 183 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 184 | << SATA_DTLE_EDGE_SHIFT); |
| 185 | } |
| 186 | |
Youness Alaoui | 696ebc2 | 2017-02-07 13:54:45 -0500 | [diff] [blame] | 187 | if (config->sata_port2_gen3_dtle) { |
| 188 | pch_iobp_update(SATA_IOBP_SP2DTLE_DATA, |
| 189 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 190 | (config->sata_port2_gen3_dtle & SATA_DTLE_MASK) |
| 191 | << SATA_DTLE_DATA_SHIFT); |
| 192 | |
| 193 | pch_iobp_update(SATA_IOBP_SP2DTLE_EDGE, |
| 194 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 195 | (config->sata_port2_gen3_dtle & SATA_DTLE_MASK) |
| 196 | << SATA_DTLE_EDGE_SHIFT); |
| 197 | } |
| 198 | if (config->sata_port3_gen3_dtle) { |
| 199 | pch_iobp_update(SATA_IOBP_SP3DTLE_DATA, |
| 200 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 201 | (config->sata_port3_gen3_dtle & SATA_DTLE_MASK) |
| 202 | << SATA_DTLE_DATA_SHIFT); |
| 203 | |
| 204 | pch_iobp_update(SATA_IOBP_SP3DTLE_EDGE, |
| 205 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 206 | (config->sata_port3_gen3_dtle & SATA_DTLE_MASK) |
| 207 | << SATA_DTLE_EDGE_SHIFT); |
| 208 | } |
| 209 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 210 | /* |
| 211 | * Additional Programming Requirements for Power Optimizer |
| 212 | */ |
| 213 | |
| 214 | /* Step 1 */ |
| 215 | sir_write(dev, 0x64, 0x883c9003); |
| 216 | |
| 217 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
| 218 | reg32 = sir_read(dev, 0x68); |
| 219 | reg32 &= 0xffff0000; |
| 220 | reg32 |= 0x880a; |
| 221 | sir_write(dev, 0x68, reg32); |
| 222 | |
| 223 | /* Step 3: SIR 60h[3] = 1 */ |
| 224 | reg32 = sir_read(dev, 0x60); |
| 225 | reg32 |= (1 << 3); |
| 226 | sir_write(dev, 0x60, reg32); |
| 227 | |
| 228 | /* Step 4: SIR 60h[0] = 1 */ |
| 229 | reg32 = sir_read(dev, 0x60); |
| 230 | reg32 |= (1 << 0); |
| 231 | sir_write(dev, 0x60, reg32); |
| 232 | |
| 233 | /* Step 5: SIR 60h[1] = 1 */ |
| 234 | reg32 = sir_read(dev, 0x60); |
| 235 | reg32 |= (1 << 1); |
| 236 | sir_write(dev, 0x60, reg32); |
| 237 | |
| 238 | /* Clock Gating */ |
| 239 | sir_write(dev, 0x70, 0x3f00bf1f); |
| 240 | sir_write(dev, 0x54, 0xcf000f0f); |
| 241 | sir_write(dev, 0x58, 0x00190000); |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 242 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 243 | |
| 244 | reg32 = pci_read_config32(dev, 0x300); |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 245 | reg32 |= (1 << 17) | (1 << 16) | (1 << 19); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 246 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
| 247 | pci_write_config32(dev, 0x300, reg32); |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 248 | |
| 249 | /* Register Lock */ |
| 250 | reg32 = pci_read_config32(dev, 0x9c); |
| 251 | reg32 |= (1 << 31); |
| 252 | pci_write_config32(dev, 0x9c, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | /* |
| 256 | * Set SATA controller mode early so the resource allocator can |
| 257 | * properly assign IO/Memory resources for the controller. |
| 258 | */ |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 259 | static void sata_enable(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 260 | { |
| 261 | /* Get the chip configuration */ |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 262 | const struct soc_intel_broadwell_pch_config *config = config_of(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 263 | u16 map = 0x0060; |
| 264 | |
Wenkai Du | 038cce2 | 2014-12-05 14:04:10 -0800 | [diff] [blame] | 265 | map |= (config->sata_port_map ^ 0xf) << 8; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 266 | |
| 267 | pci_write_config16(dev, 0x90, map); |
| 268 | } |
| 269 | |
| 270 | static struct device_operations sata_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 271 | .read_resources = pci_dev_read_resources, |
| 272 | .set_resources = pci_dev_set_resources, |
| 273 | .enable_resources = pci_dev_enable_resources, |
| 274 | .init = sata_init, |
| 275 | .enable = sata_enable, |
Angel Pons | cb2080f | 2020-10-23 15:45:44 +0200 | [diff] [blame] | 276 | .ops_pci = &pci_dev_ops_pci, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | static const unsigned short pci_device_ids[] = { |
| 280 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* LynxPoint-LP */ |
| 281 | 0x9c83, 0x9c85, 0x282a, 0x9c87, 0x282a, 0x9c8f, /* WildcatPoint */ |
| 282 | 0 |
| 283 | }; |
| 284 | |
| 285 | static const struct pci_driver pch_sata __pci_driver = { |
| 286 | .ops = &sata_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 287 | .vendor = PCI_VID_INTEL, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 288 | .devices = pci_device_ids, |
| 289 | }; |