Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 4 | * Copyright (C) 2015 - 2017 Intel Corp. |
Mario Scheithauer | a39aede | 2017-11-06 16:47:27 +0100 | [diff] [blame] | 5 | * Copyright (C) 2017 Siemens AG |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 18 | */ |
| 19 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 21 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 23 | #include <console/console.h> |
| 24 | #include <cpu/cpu.h> |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 25 | #include <cpu/x86/mp.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 26 | #include <cpu/x86/msr.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 27 | #include <device/device.h> |
| 28 | #include <device/pci.h> |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 29 | #include <intelblocks/acpi.h> |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 30 | #include <intelblocks/fast_spi.h> |
Lijian Zhao | 8aba24d | 2017-10-26 12:16:53 -0700 | [diff] [blame] | 31 | #include <intelblocks/p2sb.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 32 | #include <intelblocks/msr.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 33 | #include <fsp/api.h> |
| 34 | #include <fsp/util.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 35 | #include <intelblocks/cpulib.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 36 | #include <intelblocks/itss.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 37 | #include <intelblocks/pmclib.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 38 | #include <romstage_handoff.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 39 | #include <soc/iomap.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 40 | #include <soc/itss.h> |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 41 | #include <soc/intel/common/vbt.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 42 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 43 | #include <soc/pci_devs.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 44 | #include <spi-generic.h> |
Aaron Durbin | ac3e482 | 2017-06-14 13:21:00 -0500 | [diff] [blame] | 45 | #include <soc/cpu.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 46 | #include <soc/pm.h> |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 47 | #include <soc/systemagent.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 48 | |
| 49 | #include "chip.h" |
| 50 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 51 | static const char *soc_acpi_name(const struct device *dev) |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 52 | { |
| 53 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 54 | return "PCI0"; |
| 55 | |
| 56 | if (dev->path.type != DEVICE_PATH_PCI) |
| 57 | return NULL; |
| 58 | |
| 59 | switch (dev->path.pci.devfn) { |
| 60 | /* DSDT: acpi/northbridge.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 61 | case SA_DEVFN_ROOT: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 62 | return "MCHC"; |
| 63 | /* DSDT: acpi/lpc.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 64 | case PCH_DEVFN_LPC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 65 | return "LPCB"; |
| 66 | /* DSDT: acpi/xhci.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 67 | case PCH_DEVFN_XHCI: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 68 | return "XHCI"; |
| 69 | /* DSDT: acpi/pch_hda.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 70 | case PCH_DEVFN_HDA: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 71 | return "HDAS"; |
| 72 | /* DSDT: acpi/lpss.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 73 | case PCH_DEVFN_UART0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 74 | return "URT1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 75 | case PCH_DEVFN_UART1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 76 | return "URT2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 77 | case PCH_DEVFN_UART2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 78 | return "URT3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 79 | case PCH_DEVFN_UART3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 80 | return "URT4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 81 | case PCH_DEVFN_SPI0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 82 | return "SPI1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 83 | case PCH_DEVFN_SPI1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 84 | return "SPI2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 85 | case PCH_DEVFN_SPI2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 86 | return "SPI3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 87 | case PCH_DEVFN_PWM: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 88 | return "PWM"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 89 | case PCH_DEVFN_I2C0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 90 | return "I2C0"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 91 | case PCH_DEVFN_I2C1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 92 | return "I2C1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 93 | case PCH_DEVFN_I2C2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 94 | return "I2C2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 95 | case PCH_DEVFN_I2C3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 96 | return "I2C3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 97 | case PCH_DEVFN_I2C4: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 98 | return "I2C4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 99 | case PCH_DEVFN_I2C5: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 100 | return "I2C5"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 101 | case PCH_DEVFN_I2C6: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 102 | return "I2C6"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 103 | case PCH_DEVFN_I2C7: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 104 | return "I2C7"; |
| 105 | /* Storage */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 106 | case PCH_DEVFN_SDCARD: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 107 | return "SDCD"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 108 | case PCH_DEVFN_EMMC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 109 | return "EMMC"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 110 | case PCH_DEVFN_SDIO: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 111 | return "SDIO"; |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 112 | /* PCIe */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 113 | case PCH_DEVFN_PCIE1: |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 114 | return "RP01"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | return NULL; |
| 118 | } |
| 119 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 120 | static void pci_domain_set_resources(device_t dev) |
| 121 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 122 | assign_resources(dev->link_list); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | static struct device_operations pci_domain_ops = { |
| 126 | .read_resources = pci_domain_read_resources, |
| 127 | .set_resources = pci_domain_set_resources, |
| 128 | .enable_resources = NULL, |
| 129 | .init = NULL, |
| 130 | .scan_bus = pci_domain_scan_bus, |
| 131 | .ops_pci_bus = pci_bus_default_ops, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 132 | .acpi_name = &soc_acpi_name, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | static struct device_operations cpu_bus_ops = { |
| 136 | .read_resources = DEVICE_NOOP, |
| 137 | .set_resources = DEVICE_NOOP, |
| 138 | .enable_resources = DEVICE_NOOP, |
Aaron Durbin | ac3e482 | 2017-06-14 13:21:00 -0500 | [diff] [blame] | 139 | .init = apollolake_init_cpus, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 140 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 141 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | static void enable_dev(device_t dev) |
| 145 | { |
| 146 | /* Set the operations if it is a special bus type */ |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 147 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 148 | dev->ops = &pci_domain_ops; |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 149 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 150 | dev->ops = &cpu_bus_ops; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 151 | } |
| 152 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 153 | /* |
| 154 | * If the PCIe root port at function 0 is disabled, |
| 155 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 156 | * The below function will swap the devfn of the first enabled device |
| 157 | * in devicetree and function 0 resides a pci device |
| 158 | * so that it won't confuse coreboot. |
| 159 | */ |
| 160 | static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) |
| 161 | { |
| 162 | device_t func0; |
| 163 | unsigned int devfn; |
| 164 | int i; |
| 165 | unsigned int inc = PCI_DEVFN(0, 1); |
| 166 | |
| 167 | func0 = dev_find_slot(0, devfn0); |
| 168 | if (func0 == NULL) |
| 169 | return; |
| 170 | |
| 171 | /* No more functions if function 0 is disabled. */ |
| 172 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 173 | return; |
| 174 | |
| 175 | devfn = devfn0 + inc; |
| 176 | |
| 177 | /* |
| 178 | * Increase funtion by 1. |
| 179 | * Then find first enabled device to replace func0 |
| 180 | * as that port was move to func0. |
| 181 | */ |
| 182 | for (i = 1; i < num_funcs; i++, devfn += inc) { |
| 183 | device_t dev = dev_find_slot(0, devfn); |
| 184 | if (dev == NULL) |
| 185 | continue; |
| 186 | |
| 187 | if (!dev->enabled) |
| 188 | continue; |
| 189 | /* Found the first enabled device in given dev number */ |
| 190 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 191 | dev->path.pci.devfn = devfn0; |
| 192 | break; |
| 193 | } |
| 194 | } |
| 195 | |
| 196 | static void pcie_override_devicetree_after_silicon_init(void) |
| 197 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 198 | pcie_update_device_tree(PCH_DEVFN_PCIE1, 4); |
| 199 | pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 200 | } |
| 201 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 202 | /* Configure package power limits */ |
| 203 | static void set_power_limits(void) |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 204 | { |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 205 | static struct soc_intel_apollolake_config *cfg; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 206 | struct device *dev = SA_DEV_ROOT; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 207 | msr_t rapl_msr_reg, limit; |
| 208 | uint32_t power_unit; |
| 209 | uint32_t tdp, min_power, max_power; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 210 | uint32_t pl2_val; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 211 | |
Mario Scheithauer | 38b6100 | 2017-07-25 10:52:41 +0200 | [diff] [blame] | 212 | if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) { |
| 213 | printk(BIOS_INFO, "Skip the RAPL settings.\n"); |
| 214 | return; |
| 215 | } |
| 216 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 217 | if (!dev || !dev->chip_info) { |
| 218 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 219 | return; |
| 220 | } |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 221 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 222 | cfg = dev->chip_info; |
| 223 | |
| 224 | /* Get units */ |
| 225 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 226 | power_unit = 1 << (rapl_msr_reg.lo & 0xf); |
| 227 | |
| 228 | /* Get power defaults for this SKU */ |
| 229 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); |
| 230 | tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 231 | pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 232 | min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; |
| 233 | max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
| 234 | |
| 235 | if (min_power > 0 && tdp < min_power) |
| 236 | tdp = min_power; |
| 237 | |
| 238 | if (max_power > 0 && tdp > max_power) |
| 239 | tdp = max_power; |
| 240 | |
| 241 | /* Set PL1 override value */ |
| 242 | tdp = (cfg->tdp_pl1_override_mw == 0) ? |
| 243 | tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 244 | /* Set PL2 override value */ |
| 245 | pl2_val = (cfg->tdp_pl2_override_mw == 0) ? |
| 246 | pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 247 | |
| 248 | /* Set long term power limit to TDP */ |
| 249 | limit.lo = tdp & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 250 | /* Set PL1 Pkg Power clamp bit */ |
| 251 | limit.lo |= PKG_POWER_LIMIT_CLAMP; |
| 252 | |
| 253 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 254 | limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & |
| 255 | PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; |
| 256 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 257 | /* Set short term power limit PL2 */ |
| 258 | limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; |
| 259 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 260 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 261 | /* Program package power limits in RAPL MSR */ |
| 262 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 263 | printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, |
| 264 | 100 * (tdp % power_unit) / power_unit); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 265 | printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, |
| 266 | 100 * (pl2_val % power_unit) / power_unit); |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 267 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 268 | /* Setting RAPL MMIO register for Power limits. |
| 269 | * RAPL driver is using MSR instead of MMIO. |
| 270 | * So, disabled LIMIT_EN bit for MMIO. */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 271 | MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN; |
| 272 | MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 273 | } |
| 274 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 275 | /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ |
| 276 | static void set_sci_irq(void) |
| 277 | { |
| 278 | static struct soc_intel_apollolake_config *cfg; |
| 279 | struct device *dev = SA_DEV_ROOT; |
| 280 | uint32_t scis; |
| 281 | |
| 282 | if (!dev || !dev->chip_info) { |
| 283 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 284 | return; |
| 285 | } |
| 286 | |
| 287 | cfg = dev->chip_info; |
| 288 | |
| 289 | /* Change only if a device tree entry exists. */ |
| 290 | if (cfg->sci_irq) { |
| 291 | scis = soc_read_sci_irq_select(); |
| 292 | scis &= ~SCI_IRQ_SEL; |
| 293 | scis |= (cfg->sci_irq << SCI_IRQ_ADJUST) & SCI_IRQ_SEL; |
| 294 | soc_write_sci_irq_select(scis); |
| 295 | } |
| 296 | } |
| 297 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 298 | static void soc_init(void *data) |
| 299 | { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 300 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 301 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 302 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 303 | * default policy that doesn't honor boards' requirements. */ |
| 304 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 305 | |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 306 | fsp_silicon_init(romstage_handoff_is_resume()); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 307 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 308 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 309 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 310 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 311 | /* override 'enabled' setting in device tree if needed */ |
| 312 | pcie_override_devicetree_after_silicon_init(); |
| 313 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 314 | /* |
| 315 | * Keep the P2SB device visible so it and the other devices are |
| 316 | * visible in coreboot for driver support and PCI resource allocation. |
| 317 | * There is a UPD setting for this, but it's more consistent to use |
| 318 | * hide and unhide symmetrically. |
| 319 | */ |
| 320 | p2sb_unhide(); |
| 321 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 322 | /* Allocate ACPI NVS in CBMEM */ |
| 323 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 324 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 325 | /* Set RAPL MSR for Package power limits*/ |
| 326 | set_power_limits(); |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 327 | |
| 328 | /* |
| 329 | * FSP-S routes SCI to IRQ 9. With the help of this function you can |
| 330 | * select another IRQ for SCI. |
| 331 | */ |
| 332 | set_sci_irq(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 333 | } |
| 334 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 335 | static void soc_final(void *data) |
| 336 | { |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 337 | /* Disable global reset, just in case */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 338 | pmc_global_reset_enable(0); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 339 | /* Make sure payload/OS can't trigger global reset */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 340 | pmc_global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 341 | } |
| 342 | |
Lee Leahy | bab8be2 | 2017-03-09 09:53:58 -0800 | [diff] [blame] | 343 | static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) |
| 344 | { |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 345 | switch (dev->path.pci.devfn) { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 346 | case PCH_DEVFN_ISH: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 347 | silconfig->IshEnable = 0; |
| 348 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 349 | case PCH_DEVFN_SATA: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 350 | silconfig->EnableSata = 0; |
| 351 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 352 | case PCH_DEVFN_PCIE5: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 353 | silconfig->PcieRootPortEn[0] = 0; |
| 354 | silconfig->PcieRpHotPlug[0] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 355 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 356 | case PCH_DEVFN_PCIE6: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 357 | silconfig->PcieRootPortEn[1] = 0; |
| 358 | silconfig->PcieRpHotPlug[1] = 0; |
| 359 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 360 | case PCH_DEVFN_PCIE1: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 361 | silconfig->PcieRootPortEn[2] = 0; |
| 362 | silconfig->PcieRpHotPlug[2] = 0; |
| 363 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 364 | case PCH_DEVFN_PCIE2: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 365 | silconfig->PcieRootPortEn[3] = 0; |
| 366 | silconfig->PcieRpHotPlug[3] = 0; |
| 367 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 368 | case PCH_DEVFN_PCIE3: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 369 | silconfig->PcieRootPortEn[4] = 0; |
| 370 | silconfig->PcieRpHotPlug[4] = 0; |
| 371 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 372 | case PCH_DEVFN_PCIE4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 373 | silconfig->PcieRootPortEn[5] = 0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 374 | silconfig->PcieRpHotPlug[5] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 375 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 376 | case PCH_DEVFN_XHCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 377 | silconfig->Usb30Mode = 0; |
| 378 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 379 | case PCH_DEVFN_XDCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 380 | silconfig->UsbOtg = 0; |
| 381 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 382 | case PCH_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 383 | silconfig->I2c0Enable = 0; |
| 384 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 385 | case PCH_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 386 | silconfig->I2c1Enable = 0; |
| 387 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 388 | case PCH_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 389 | silconfig->I2c2Enable = 0; |
| 390 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 391 | case PCH_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 392 | silconfig->I2c3Enable = 0; |
| 393 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 394 | case PCH_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 395 | silconfig->I2c4Enable = 0; |
| 396 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 397 | case PCH_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 398 | silconfig->I2c5Enable = 0; |
| 399 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 400 | case PCH_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 401 | silconfig->I2c6Enable = 0; |
| 402 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 403 | case PCH_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 404 | silconfig->I2c7Enable = 0; |
| 405 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 406 | case PCH_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 407 | silconfig->Hsuart0Enable = 0; |
| 408 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 409 | case PCH_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 410 | silconfig->Hsuart1Enable = 0; |
| 411 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 412 | case PCH_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 413 | silconfig->Hsuart2Enable = 0; |
| 414 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 415 | case PCH_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 416 | silconfig->Hsuart3Enable = 0; |
| 417 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 418 | case PCH_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 419 | silconfig->Spi0Enable = 0; |
| 420 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 421 | case PCH_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 422 | silconfig->Spi1Enable = 0; |
| 423 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 424 | case PCH_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 425 | silconfig->Spi2Enable = 0; |
| 426 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 427 | case PCH_DEVFN_SDCARD: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 428 | silconfig->SdcardEnabled = 0; |
| 429 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 430 | case PCH_DEVFN_EMMC: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 431 | silconfig->eMMCEnabled = 0; |
| 432 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 433 | case PCH_DEVFN_SDIO: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 434 | silconfig->SdioEnabled = 0; |
| 435 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 436 | case PCH_DEVFN_SMBUS: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 437 | silconfig->SmbusEnable = 0; |
| 438 | break; |
| 439 | default: |
| 440 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 441 | PCI_SLOT(dev->path.pci.devfn), |
| 442 | PCI_FUNC(dev->path.pci.devfn)); |
| 443 | break; |
| 444 | } |
| 445 | } |
| 446 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 447 | static void parse_devicetree(FSP_S_CONFIG *silconfig) |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 448 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 449 | struct device *dev = SA_DEV_ROOT; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 450 | |
| 451 | if (!dev) { |
| 452 | printk(BIOS_ERR, "Could not find root device\n"); |
| 453 | return; |
| 454 | } |
| 455 | /* Only disable bus 0 devices. */ |
| 456 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 457 | if (!dev->enabled) |
| 458 | disable_dev(dev, silconfig); |
| 459 | } |
| 460 | } |
| 461 | |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 462 | static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config |
| 463 | *cfg, FSP_S_CONFIG *silconfig) |
| 464 | { |
| 465 | #if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* GLK FSP does not have these |
| 466 | fields in FspsUpd.h yet */ |
| 467 | uint8_t port; |
| 468 | |
| 469 | for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { |
| 470 | if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) |
| 471 | silconfig->PortUsb20PerPortTxPeHalf[port] = |
| 472 | cfg->usb2eye[port].Usb20PerPortTxPeHalf; |
| 473 | |
| 474 | if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0) |
| 475 | silconfig->PortUsb20PerPortPeTxiSet[port] = |
| 476 | cfg->usb2eye[port].Usb20PerPortPeTxiSet; |
| 477 | |
| 478 | if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0) |
| 479 | silconfig->PortUsb20PerPortTxiSet[port] = |
| 480 | cfg->usb2eye[port].Usb20PerPortTxiSet; |
| 481 | |
| 482 | if (cfg->usb2eye[port].Usb20HsSkewSel != 0) |
| 483 | silconfig->PortUsb20HsSkewSel[port] = |
| 484 | cfg->usb2eye[port].Usb20HsSkewSel; |
| 485 | |
| 486 | if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0) |
| 487 | silconfig->PortUsb20IUsbTxEmphasisEn[port] = |
| 488 | cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; |
| 489 | |
| 490 | if (cfg->usb2eye[port].Usb20PerPortRXISet != 0) |
| 491 | silconfig->PortUsb20PerPortRXISet[port] = |
| 492 | cfg->usb2eye[port].Usb20PerPortRXISet; |
| 493 | |
| 494 | if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0) |
| 495 | silconfig->PortUsb20HsNpreDrvSel[port] = |
| 496 | cfg->usb2eye[port].Usb20HsNpreDrvSel; |
| 497 | } |
| 498 | #endif |
| 499 | } |
| 500 | |
| 501 | static void glk_fsp_silicon_init_params_cb( |
| 502 | struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) |
| 503 | { |
| 504 | silconfig->Gmm = 0; |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 505 | } |
| 506 | |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 507 | void __attribute__((weak)) mainboard_devtree_update(struct device *dev) |
| 508 | { |
| 509 | /* Override dev tree settings per board */ |
| 510 | } |
| 511 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 512 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 513 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 514 | FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 515 | static struct soc_intel_apollolake_config *cfg; |
| 516 | |
| 517 | /* Load VBT before devicetree-specific config. */ |
Patrick Georgi | 2257959 | 2017-10-06 17:36:09 +0200 | [diff] [blame] | 518 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 519 | |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 520 | struct device *dev = SA_DEV_ROOT; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 521 | |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 522 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 523 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 524 | return; |
| 525 | } |
| 526 | |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 527 | mainboard_devtree_update(dev); |
| 528 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 529 | cfg = dev->chip_info; |
| 530 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 531 | /* Parse device tree and disable unused device*/ |
| 532 | parse_devicetree(silconfig); |
| 533 | |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame^] | 534 | memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, |
| 535 | sizeof(silconfig->PcieRpClkReqNumber)); |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 536 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 537 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 538 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 539 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 540 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 541 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 542 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 543 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 544 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 545 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 546 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 547 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 548 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
| 549 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 550 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 551 | |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 552 | /* Disable monitor mwait since it is broken due to a hardware bug |
| 553 | * without a fix |
| 554 | */ |
Bora Guvendik | 60cc75d | 2016-07-25 14:44:51 -0700 | [diff] [blame] | 555 | silconfig->MonitorMwaitEnable = 0; |
| 556 | |
Venkateswarlu Vinjamuri | 1a5e32c | 2016-10-31 17:15:30 -0700 | [diff] [blame] | 557 | silconfig->SkipMpInit = 1; |
| 558 | |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 559 | /* Disable setting of EISS bit in FSP. */ |
| 560 | silconfig->SpiEiss = 0; |
Ravi Sarawadi | 3a21d0f | 2016-08-10 11:33:56 -0700 | [diff] [blame] | 561 | |
| 562 | /* Disable FSP from locking access to the RTC NVRAM */ |
| 563 | silconfig->RtcLock = 0; |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 564 | |
| 565 | /* Enable Audio clk gate and power gate */ |
| 566 | silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |
| 567 | silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; |
| 568 | /* Bios config lockdown Audio clk and power gate */ |
| 569 | silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 570 | if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) |
| 571 | glk_fsp_silicon_init_params_cb(cfg, silconfig); |
| 572 | else |
| 573 | apl_fsp_silicon_init_params_cb(cfg, silconfig); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | struct chip_operations soc_intel_apollolake_ops = { |
| 577 | CHIP_NAME("Intel Apollolake SOC") |
| 578 | .enable_dev = &enable_dev, |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 579 | .init = &soc_init, |
| 580 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 581 | }; |
| 582 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 583 | static void drop_privilege_all(void) |
| 584 | { |
| 585 | /* Drop privilege level on all the CPUs */ |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 586 | if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, 1000) < 0) |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 587 | printk(BIOS_ERR, "failed to enable untrusted mode\n"); |
| 588 | } |
| 589 | |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 590 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 591 | { |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 592 | if (phase == END_OF_FIRMWARE) { |
| 593 | /* Hide the P2SB device to align with previous behavior. */ |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 594 | p2sb_hide(); |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 595 | /* |
| 596 | * As per guidelines BIOS is recommended to drop CPU privilege |
| 597 | * level to IA_UNTRUSTED. After that certain device registers |
| 598 | * and MSRs become inaccessible supposedly increasing system |
| 599 | * security. |
| 600 | */ |
| 601 | drop_privilege_all(); |
| 602 | } |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 603 | } |
| 604 | |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 605 | /* |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 606 | * spi_flash init() needs to run unconditionally on every boot (including |
| 607 | * resume) to allow write protect to be disabled for eventlog and nvram |
| 608 | * updates. This needs to be done as early as possible in ramstage. Thus, add a |
| 609 | * callback for entry into BS_PRE_DEVICE. |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 610 | */ |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 611 | static void spi_flash_init_cb(void *unused) |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 612 | { |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 613 | fast_spi_init(); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 614 | } |
| 615 | |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 616 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); |