Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 2 | |
Martin Roth | cddd600 | 2019-09-23 17:38:27 -0600 | [diff] [blame] | 3 | /* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */ |
| 4 | |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 7 | #include <device/mmio.h> |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 8 | #include <device/path.h> |
| 9 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 11 | #include <device/pci_ids.h> |
| 12 | #include "chip.h" |
Kevin Chiu | 089b685 | 2018-08-03 18:52:18 +0800 | [diff] [blame] | 13 | #include "bh720.h" |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 14 | |
Angel Pons | 42e4433 | 2021-01-26 11:11:13 +0100 | [diff] [blame] | 15 | static u32 bh720_read_pcr(u32 sdbar, u32 addr) |
| 16 | { |
| 17 | write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | addr); |
| 18 | return read32((void *)(sdbar + BH720_MEM_RW_DATA)); |
| 19 | } |
| 20 | |
| 21 | static void bh720_write_pcr(u32 sdbar, u32 addr, u32 data) |
| 22 | { |
| 23 | write32((void *)(sdbar + BH720_MEM_RW_DATA), data); |
| 24 | write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | addr); |
| 25 | } |
| 26 | |
| 27 | static void bh720_rmw_pcr(u32 sdbar, u32 addr, u32 clear, u32 set) |
| 28 | { |
| 29 | u32 data = bh720_read_pcr(sdbar, addr); |
| 30 | data &= ~clear; |
| 31 | data |= set; |
| 32 | bh720_write_pcr(sdbar, addr, data); |
| 33 | } |
| 34 | |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 35 | static void bh720_program_hs200_mode(struct device *dev) |
Kevin Chiu | 089b685 | 2018-08-03 18:52:18 +0800 | [diff] [blame] | 36 | { |
Angel Pons | 42e4433 | 2021-01-26 11:11:13 +0100 | [diff] [blame] | 37 | u32 sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 38 | |
| 39 | /* Enable Memory Access Function */ |
| 40 | write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); |
Angel Pons | 42e4433 | 2021-01-26 11:11:13 +0100 | [diff] [blame] | 41 | bh720_write_pcr(sdbar, 0xd0, 0x80000000); |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 42 | |
| 43 | /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ |
Angel Pons | 42e4433 | 2021-01-26 11:11:13 +0100 | [diff] [blame] | 44 | bh720_rmw_pcr(sdbar, BH720_PCR_EMMC_SETTING, 0, BH720_PCR_EMMC_SETTING_1_8V); |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 45 | |
| 46 | /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ |
Angel Pons | 42e4433 | 2021-01-26 11:11:13 +0100 | [diff] [blame] | 47 | bh720_rmw_pcr(sdbar, BH720_PCR_DrvStrength_PLL, 0xffff << 16, 0x2510 << 16); |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 48 | |
| 49 | /* Use PLL Base clock PCR 0x3E4[22] = 1 */ |
Angel Pons | 42e4433 | 2021-01-26 11:11:13 +0100 | [diff] [blame] | 50 | bh720_rmw_pcr(sdbar, BH720_PCR_CSR, 0, BH720_PCR_CSR_EMMC_MODE_SEL); |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 51 | |
| 52 | /* Disable Memory Access */ |
Angel Pons | 42e4433 | 2021-01-26 11:11:13 +0100 | [diff] [blame] | 53 | bh720_write_pcr(sdbar, 0xd0, 0x80000001); |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 54 | write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); |
Kevin Chiu | 089b685 | 2018-08-03 18:52:18 +0800 | [diff] [blame] | 55 | } |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 56 | |
| 57 | static void bh720_init(struct device *dev) |
| 58 | { |
| 59 | struct drivers_generic_bayhub_config *config = dev->chip_info; |
| 60 | |
| 61 | pci_dev_init(dev); |
| 62 | |
| 63 | if (config && config->power_saving) { |
| 64 | /* |
| 65 | * This procedure for enabling power-saving mode is from the |
| 66 | * BayHub BIOS Implementation Guideline document. |
| 67 | */ |
Simon Glass | 4f16049 | 2018-05-23 15:34:04 -0600 | [diff] [blame] | 68 | pci_write_config32(dev, BH720_PROTECT, |
| 69 | BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF); |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 70 | pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1); |
| 71 | pci_or_config32(dev, BH720_LINK_CTRL, |
| 72 | BH720_LINK_CTRL_L0_ENABLE | |
| 73 | BH720_LINK_CTRL_L1_ENABLE); |
| 74 | pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ); |
Simon Glass | 4f16049 | 2018-05-23 15:34:04 -0600 | [diff] [blame] | 75 | pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE, |
| 76 | BH720_MISC2_APSM_CLKREQ_L1 | |
| 77 | BH720_MISC2_APSM_PHY_L1); |
| 78 | pci_write_config32(dev, BH720_PROTECT, |
| 79 | BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); |
| 80 | |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 81 | printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n", |
| 82 | pci_read_config32(dev, BH720_LINK_CTRL)); |
| 83 | } |
Kevin Chiu | 089b685 | 2018-08-03 18:52:18 +0800 | [diff] [blame] | 84 | |
Angel Pons | 73c9676 | 2021-01-22 15:24:48 +0100 | [diff] [blame] | 85 | if (config && !config->disable_hs200_mode) |
| 86 | bh720_program_hs200_mode(dev); |
Angel Pons | e4abe7f | 2021-01-22 15:12:14 +0100 | [diff] [blame] | 87 | |
| 88 | if (config && config->vih_tuning_value) { |
| 89 | /* Tune VIH */ |
| 90 | u32 bh720_pcr_data; |
| 91 | pci_write_config32(dev, BH720_PROTECT, |
| 92 | BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF); |
| 93 | bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL); |
| 94 | bh720_pcr_data &= 0xFFFFFF00; |
| 95 | bh720_pcr_data |= config->vih_tuning_value; |
| 96 | pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data); |
| 97 | pci_write_config32(dev, BH720_PROTECT, |
| 98 | BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); |
| 99 | } |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 100 | } |
| 101 | |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 102 | static struct device_operations bh720_ops = { |
| 103 | .read_resources = pci_dev_read_resources, |
| 104 | .set_resources = pci_dev_set_resources, |
| 105 | .enable_resources = pci_dev_enable_resources, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 106 | .ops_pci = &pci_dev_ops_pci, |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 107 | .init = bh720_init, |
| 108 | }; |
| 109 | |
| 110 | static const unsigned short pci_device_ids[] = { |
| 111 | PCI_DEVICE_ID_O2_BH720, |
| 112 | 0 |
| 113 | }; |
| 114 | |
| 115 | static const struct pci_driver bayhub_bh720 __pci_driver = { |
| 116 | .ops = &bh720_ops, |
| 117 | .vendor = PCI_VENDOR_ID_O2, |
| 118 | .devices = pci_device_ids, |
| 119 | }; |
| 120 | |
Kyösti Mälkki | 08c76e1 | 2019-08-25 13:05:46 +0300 | [diff] [blame] | 121 | struct chip_operations drivers_generic_bayhub_ops = { |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 122 | CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge") |
Simon Glass | 38d875f | 2018-04-30 14:08:31 -0600 | [diff] [blame] | 123 | }; |