blob: b689b679d0080d928d211f3448fecf2efc28afe3 [file] [log] [blame]
Simon Glass38d875f2018-04-30 14:08:31 -06001/*
2 * Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge
3 *
4 * This file is part of the coreboot project.
5 *
6 * Copyright 2018 Google LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <console/console.h>
19#include <device/device.h>
20#include <device/path.h>
21#include <device/pci.h>
22#include <device/pci_ids.h>
23#include "chip.h"
Kevin Chiu089b6852018-08-03 18:52:18 +080024#include "bh720.h"
Simon Glass38d875f2018-04-30 14:08:31 -060025
Kevin Chiu089b6852018-08-03 18:52:18 +080026__attribute__((weak)) void bh720_driving_strength(struct device *dev)
27{
28}
Simon Glass38d875f2018-04-30 14:08:31 -060029
30static void bh720_init(struct device *dev)
31{
32 struct drivers_generic_bayhub_config *config = dev->chip_info;
33
34 pci_dev_init(dev);
35
36 if (config && config->power_saving) {
37 /*
38 * This procedure for enabling power-saving mode is from the
39 * BayHub BIOS Implementation Guideline document.
40 */
Simon Glass4f160492018-05-23 15:34:04 -060041 pci_write_config32(dev, BH720_PROTECT,
42 BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
Simon Glass38d875f2018-04-30 14:08:31 -060043 pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1);
44 pci_or_config32(dev, BH720_LINK_CTRL,
45 BH720_LINK_CTRL_L0_ENABLE |
46 BH720_LINK_CTRL_L1_ENABLE);
47 pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ);
Simon Glass4f160492018-05-23 15:34:04 -060048 pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE,
49 BH720_MISC2_APSM_CLKREQ_L1 |
50 BH720_MISC2_APSM_PHY_L1);
51 pci_write_config32(dev, BH720_PROTECT,
52 BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
53
Simon Glass38d875f2018-04-30 14:08:31 -060054 printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
55 pci_read_config32(dev, BH720_LINK_CTRL));
56 }
Kevin Chiu089b6852018-08-03 18:52:18 +080057
58 bh720_driving_strength(dev);
Simon Glass38d875f2018-04-30 14:08:31 -060059}
60
61static struct pci_operations pci_ops = {
62 .set_subsystem = pci_dev_set_subsystem,
63};
64
65static struct device_operations bh720_ops = {
66 .read_resources = pci_dev_read_resources,
67 .set_resources = pci_dev_set_resources,
68 .enable_resources = pci_dev_enable_resources,
69 .ops_pci = &pci_ops,
70 .init = bh720_init,
71};
72
73static const unsigned short pci_device_ids[] = {
74 PCI_DEVICE_ID_O2_BH720,
75 0
76};
77
78static const struct pci_driver bayhub_bh720 __pci_driver = {
79 .ops = &bh720_ops,
80 .vendor = PCI_VENDOR_ID_O2,
81 .devices = pci_device_ids,
82};
83
84static void bh720_enable(struct device *dev)
85{
86 dev->ops = &bh720_ops;
87}
88
89struct chip_operations bayhub_bh720_ops = {
90 CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge")
91 .enable_dev = bh720_enable,
92};