blob: 24386642ebff2af6f6c851c1f57fbd22dda59e02 [file] [log] [blame]
Angel Pons8a3453f2020-04-02 23:48:19 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Simon Glass38d875f2018-04-30 14:08:31 -06002
Martin Rothcddd6002019-09-23 17:38:27 -06003/* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */
4
Simon Glass38d875f2018-04-30 14:08:31 -06005#include <console/console.h>
6#include <device/device.h>
7#include <device/path.h>
8#include <device/pci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02009#include <device/pci_ops.h>
Simon Glass38d875f2018-04-30 14:08:31 -060010#include <device/pci_ids.h>
11#include "chip.h"
Kevin Chiu089b6852018-08-03 18:52:18 +080012#include "bh720.h"
Simon Glass38d875f2018-04-30 14:08:31 -060013
Kevin Chiu328ff7d2018-08-27 11:44:46 +080014__attribute__((weak)) void board_bh720(struct device *dev)
Kevin Chiu089b6852018-08-03 18:52:18 +080015{
16}
Simon Glass38d875f2018-04-30 14:08:31 -060017
18static void bh720_init(struct device *dev)
19{
20 struct drivers_generic_bayhub_config *config = dev->chip_info;
21
22 pci_dev_init(dev);
23
24 if (config && config->power_saving) {
25 /*
26 * This procedure for enabling power-saving mode is from the
27 * BayHub BIOS Implementation Guideline document.
28 */
Simon Glass4f160492018-05-23 15:34:04 -060029 pci_write_config32(dev, BH720_PROTECT,
30 BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
Simon Glass38d875f2018-04-30 14:08:31 -060031 pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1);
32 pci_or_config32(dev, BH720_LINK_CTRL,
33 BH720_LINK_CTRL_L0_ENABLE |
34 BH720_LINK_CTRL_L1_ENABLE);
35 pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ);
Simon Glass4f160492018-05-23 15:34:04 -060036 pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE,
37 BH720_MISC2_APSM_CLKREQ_L1 |
38 BH720_MISC2_APSM_PHY_L1);
39 pci_write_config32(dev, BH720_PROTECT,
40 BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
41
Simon Glass38d875f2018-04-30 14:08:31 -060042 printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
43 pci_read_config32(dev, BH720_LINK_CTRL));
44 }
Kevin Chiu089b6852018-08-03 18:52:18 +080045
Kevin Chiu328ff7d2018-08-27 11:44:46 +080046 board_bh720(dev);
Angel Ponse4abe7f2021-01-22 15:12:14 +010047
48 if (config && config->vih_tuning_value) {
49 /* Tune VIH */
50 u32 bh720_pcr_data;
51 pci_write_config32(dev, BH720_PROTECT,
52 BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
53 bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
54 bh720_pcr_data &= 0xFFFFFF00;
55 bh720_pcr_data |= config->vih_tuning_value;
56 pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
57 pci_write_config32(dev, BH720_PROTECT,
58 BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
59 }
Simon Glass38d875f2018-04-30 14:08:31 -060060}
61
Simon Glass38d875f2018-04-30 14:08:31 -060062static struct device_operations bh720_ops = {
63 .read_resources = pci_dev_read_resources,
64 .set_resources = pci_dev_set_resources,
65 .enable_resources = pci_dev_enable_resources,
Angel Pons1fc0edd2020-05-31 00:03:28 +020066 .ops_pci = &pci_dev_ops_pci,
Simon Glass38d875f2018-04-30 14:08:31 -060067 .init = bh720_init,
68};
69
70static const unsigned short pci_device_ids[] = {
71 PCI_DEVICE_ID_O2_BH720,
72 0
73};
74
75static const struct pci_driver bayhub_bh720 __pci_driver = {
76 .ops = &bh720_ops,
77 .vendor = PCI_VENDOR_ID_O2,
78 .devices = pci_device_ids,
79};
80
Kyösti Mälkki08c76e12019-08-25 13:05:46 +030081struct chip_operations drivers_generic_bayhub_ops = {
Simon Glass38d875f2018-04-30 14:08:31 -060082 CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge")
Simon Glass38d875f2018-04-30 14:08:31 -060083};