blob: 43a169b5429b0cfc767b0510003d25f15fe7df87 [file] [log] [blame]
Angel Pons8a3453f2020-04-02 23:48:19 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Simon Glass38d875f2018-04-30 14:08:31 -06003
Martin Rothcddd6002019-09-23 17:38:27 -06004/* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */
5
Simon Glass38d875f2018-04-30 14:08:31 -06006#include <console/console.h>
7#include <device/device.h>
8#include <device/path.h>
9#include <device/pci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020010#include <device/pci_ops.h>
Simon Glass38d875f2018-04-30 14:08:31 -060011#include <device/pci_ids.h>
12#include "chip.h"
Kevin Chiu089b6852018-08-03 18:52:18 +080013#include "bh720.h"
Simon Glass38d875f2018-04-30 14:08:31 -060014
Kevin Chiu328ff7d2018-08-27 11:44:46 +080015__attribute__((weak)) void board_bh720(struct device *dev)
Kevin Chiu089b6852018-08-03 18:52:18 +080016{
17}
Simon Glass38d875f2018-04-30 14:08:31 -060018
19static void bh720_init(struct device *dev)
20{
21 struct drivers_generic_bayhub_config *config = dev->chip_info;
22
23 pci_dev_init(dev);
24
25 if (config && config->power_saving) {
26 /*
27 * This procedure for enabling power-saving mode is from the
28 * BayHub BIOS Implementation Guideline document.
29 */
Simon Glass4f160492018-05-23 15:34:04 -060030 pci_write_config32(dev, BH720_PROTECT,
31 BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
Simon Glass38d875f2018-04-30 14:08:31 -060032 pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1);
33 pci_or_config32(dev, BH720_LINK_CTRL,
34 BH720_LINK_CTRL_L0_ENABLE |
35 BH720_LINK_CTRL_L1_ENABLE);
36 pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ);
Simon Glass4f160492018-05-23 15:34:04 -060037 pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE,
38 BH720_MISC2_APSM_CLKREQ_L1 |
39 BH720_MISC2_APSM_PHY_L1);
40 pci_write_config32(dev, BH720_PROTECT,
41 BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
42
Simon Glass38d875f2018-04-30 14:08:31 -060043 printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
44 pci_read_config32(dev, BH720_LINK_CTRL));
45 }
Kevin Chiu089b6852018-08-03 18:52:18 +080046
Kevin Chiu328ff7d2018-08-27 11:44:46 +080047 board_bh720(dev);
Simon Glass38d875f2018-04-30 14:08:31 -060048}
49
50static struct pci_operations pci_ops = {
51 .set_subsystem = pci_dev_set_subsystem,
52};
53
54static struct device_operations bh720_ops = {
55 .read_resources = pci_dev_read_resources,
56 .set_resources = pci_dev_set_resources,
57 .enable_resources = pci_dev_enable_resources,
58 .ops_pci = &pci_ops,
59 .init = bh720_init,
60};
61
62static const unsigned short pci_device_ids[] = {
63 PCI_DEVICE_ID_O2_BH720,
64 0
65};
66
67static const struct pci_driver bayhub_bh720 __pci_driver = {
68 .ops = &bh720_ops,
69 .vendor = PCI_VENDOR_ID_O2,
70 .devices = pci_device_ids,
71};
72
Kyösti Mälkki08c76e12019-08-25 13:05:46 +030073struct chip_operations drivers_generic_bayhub_ops = {
Simon Glass38d875f2018-04-30 14:08:31 -060074 CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge")
Simon Glass38d875f2018-04-30 14:08:31 -060075};