Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef _HUDSON_EARLY_SETUP_C_ |
| 17 | #define _HUDSON_EARLY_SETUP_C_ |
| 18 | |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 19 | #include <assert.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 20 | #include <stdint.h> |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame^] | 21 | #include <amdblocks/acpimmio.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 22 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 24 | #include <console/console.h> |
Kyösti Mälkki | a244d5e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 25 | #include <amdblocks/acpimmio.h> |
Elyes HAOUAS | eb789f0 | 2018-10-27 16:40:25 +0200 | [diff] [blame] | 26 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 27 | #include "hudson.h" |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 28 | #include "pci_devs.h" |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 29 | #include <Fch/Fch.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 30 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 31 | #if CONFIG(HUDSON_UART) |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 32 | |
| 33 | #include <cpu/x86/msr.h> |
| 34 | #include <delay.h> |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 35 | |
| 36 | void configure_hudson_uart(void) |
| 37 | { |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 38 | u8 byte; |
| 39 | |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame^] | 40 | byte = aoac_read8(FCH_AOAC_REG56 + |
| 41 | CONFIG_UART_FOR_CONSOLE * sizeof(u16))); |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 42 | byte |= 1 << 3; |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame^] | 43 | aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), |
| 44 | byte); |
| 45 | |
| 46 | aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3)); |
| 47 | iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */ |
| 48 | iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */ |
| 49 | iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */ |
| 50 | iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */ |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 51 | |
| 52 | udelay(2000); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 53 | write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88), |
| 54 | 0x01); /* reset UART */ |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | #endif |
| 58 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 59 | void hudson_pci_port80(void) |
| 60 | { |
| 61 | u8 byte; |
Antonello Dettori | 1ac9728 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 62 | pci_devfn_t dev; |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 63 | |
| 64 | /* P2P Bridge */ |
| 65 | dev = PCI_DEV(0, 0x14, 4); |
| 66 | |
| 67 | /* Chip Control: Enable subtractive decoding */ |
| 68 | byte = pci_read_config8(dev, 0x40); |
| 69 | byte |= 1 << 5; |
| 70 | pci_write_config8(dev, 0x40, byte); |
| 71 | |
| 72 | /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ |
| 73 | byte = pci_read_config8(dev, 0x4B); |
| 74 | byte |= 1 << 7; |
| 75 | pci_write_config8(dev, 0x4B, byte); |
| 76 | |
| 77 | /* The same IO Base and IO Limit here is meaningful because we set the |
| 78 | * bridge to be subtractive. During early setup stage, we have to make |
| 79 | * sure that data can go through port 0x80. |
| 80 | */ |
| 81 | /* IO Base: 0xf000 */ |
| 82 | byte = pci_read_config8(dev, 0x1C); |
| 83 | byte |= 0xF << 4; |
| 84 | pci_write_config8(dev, 0x1C, byte); |
| 85 | |
| 86 | /* IO Limit: 0xf000 */ |
| 87 | byte = pci_read_config8(dev, 0x1D); |
| 88 | byte |= 0xF << 4; |
| 89 | pci_write_config8(dev, 0x1D, byte); |
| 90 | |
| 91 | /* PCI Command: Enable IO response */ |
| 92 | byte = pci_read_config8(dev, 0x04); |
| 93 | byte |= 1 << 0; |
| 94 | pci_write_config8(dev, 0x04, byte); |
| 95 | |
| 96 | /* LPC controller */ |
| 97 | dev = PCI_DEV(0, 0x14, 3); |
| 98 | |
| 99 | byte = pci_read_config8(dev, 0x4A); |
| 100 | byte &= ~(1 << 5); /* disable lpc port 80 */ |
| 101 | pci_write_config8(dev, 0x4A, byte); |
| 102 | } |
| 103 | |
| 104 | void hudson_lpc_port80(void) |
| 105 | { |
| 106 | u8 byte; |
Antonello Dettori | 1ac9728 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 107 | pci_devfn_t dev; |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 108 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 109 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
| 110 | dev = PCI_DEV(0, 0x14, 3); |
| 111 | byte = pci_read_config8(dev, 0x4a); |
| 112 | byte |= 1 << 5; /* enable port 80 */ |
| 113 | pci_write_config8(dev, 0x4a, byte); |
| 114 | } |
| 115 | |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 116 | void hudson_lpc_decode(void) |
| 117 | { |
Antonello Dettori | 1ac9728 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 118 | pci_devfn_t dev; |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 119 | u32 tmp; |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 120 | |
Kyösti Mälkki | a244d5e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 121 | /* Enable LPC controller */ |
| 122 | pm_write8(0xec, pm_read8(0xec) | 0x01); |
| 123 | |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 124 | dev = PCI_DEV(0, 0x14, 3); |
| 125 | /* Serial port numeration on Hudson: |
| 126 | * PORT0 - 0x3f8 |
| 127 | * PORT1 - 0x2f8 |
| 128 | * PORT5 - 0x2e8 |
| 129 | * PORT7 - 0x3e8 |
| 130 | */ |
| 131 | tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 |
| 132 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 133 | |
| 134 | pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); |
| 135 | } |
| 136 | |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 137 | static void enable_wideio(uint8_t port, uint16_t size) |
| 138 | { |
| 139 | uint32_t wideio_enable[] = { |
| 140 | LPC_WIDEIO0_ENABLE, |
| 141 | LPC_WIDEIO1_ENABLE, |
| 142 | LPC_WIDEIO2_ENABLE |
| 143 | }; |
| 144 | uint32_t alt_wideio_enable[] = { |
| 145 | LPC_ALT_WIDEIO0_ENABLE, |
| 146 | LPC_ALT_WIDEIO1_ENABLE, |
| 147 | LPC_ALT_WIDEIO2_ENABLE |
| 148 | }; |
| 149 | pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); |
| 150 | uint32_t tmp; |
| 151 | |
| 152 | /* Only allow port 0-2 */ |
| 153 | assert(port <= ARRAY_SIZE(wideio_enable)); |
| 154 | |
| 155 | if (size == 16) { |
| 156 | tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 157 | tmp |= alt_wideio_enable[port]; |
| 158 | pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 159 | } else { /* 512 */ |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 160 | tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 161 | tmp &= ~alt_wideio_enable[port]; |
| 162 | pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); |
| 163 | } |
| 164 | |
| 165 | /* Enable the range */ |
| 166 | tmp = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 167 | tmp |= wideio_enable[port]; |
| 168 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); |
| 169 | } |
| 170 | |
| 171 | /* |
| 172 | * lpc_wideio_window() may be called any point in romstage, but take |
| 173 | * care that AGESA doesn't overwrite the range this function used. |
| 174 | * The function checks if there is an empty range and if all ranges are |
| 175 | * used the function throws an assert. The function doesn't check for a |
| 176 | * duplicate range, for ranges that can be merged into a single |
| 177 | * range, or ranges that overlap. |
| 178 | * |
| 179 | * The developer is expected to ensure that there are no conflicts. |
| 180 | */ |
| 181 | static void lpc_wideio_window(uint16_t base, uint16_t size) |
| 182 | { |
| 183 | pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); |
| 184 | u32 tmp; |
| 185 | |
| 186 | /* Support 512 or 16 bytes per range */ |
| 187 | assert(size == 512 || size == 16); |
| 188 | |
| 189 | /* Find and open Base Register and program it */ |
| 190 | tmp = pci_read_config32(dev, LPC_WIDEIO_GENERIC_PORT); |
| 191 | |
| 192 | if ((tmp & 0xFFFF) == 0) { /* WIDEIO0 */ |
| 193 | tmp |= base; |
| 194 | pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); |
| 195 | enable_wideio(0, size); |
| 196 | } else if ((tmp & 0xFFFF0000) == 0) { /* WIDEIO1 */ |
| 197 | tmp |= (base << 16); |
| 198 | pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); |
| 199 | enable_wideio(1, size); |
| 200 | } else { /* Check WIDEIO2 register */ |
| 201 | tmp = pci_read_config32(dev, LPC_WIDEIO2_GENERIC_PORT); |
| 202 | if ((tmp & 0xFFFF) == 0) { /* WIDEIO2 */ |
| 203 | tmp |= base; |
| 204 | pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp); |
| 205 | enable_wideio(2, size); |
| 206 | } else { /* All WIDEIO locations used*/ |
| 207 | assert(0); |
| 208 | } |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | void lpc_wideio_512_window(uint16_t base) |
| 213 | { |
| 214 | assert(IS_ALIGNED(base, 512)); |
| 215 | lpc_wideio_window(base, 512); |
| 216 | } |
| 217 | |
| 218 | void lpc_wideio_16_window(uint16_t base) |
| 219 | { |
| 220 | assert(IS_ALIGNED(base, 16)); |
| 221 | lpc_wideio_window(base, 16); |
| 222 | } |
| 223 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 224 | void hudson_clk_output_48Mhz(void) |
| 225 | { |
Marshall Dawson | 0bf3f55 | 2017-07-13 12:06:25 -0600 | [diff] [blame] | 226 | u32 ctrl; |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 227 | |
| 228 | /* |
| 229 | * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so |
| 230 | * 48Mhz will be on ball AP13 (FT3b package) |
| 231 | */ |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame^] | 232 | ctrl = misc_read32(FCH_MISC_REG40); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 233 | |
| 234 | /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ |
Marshall Dawson | 0bf3f55 | 2017-07-13 12:06:25 -0600 | [diff] [blame] | 235 | ctrl &= (u32)~(1<<2); |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame^] | 236 | misc_write32(FCH_MISC_REG40, ctrl); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 237 | } |
| 238 | |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 239 | static uintptr_t hudson_spibase(void) |
| 240 | { |
| 241 | /* Make sure the base address is predictable */ |
Elyes HAOUAS | d9ef546 | 2018-05-19 17:08:23 +0200 | [diff] [blame] | 242 | pci_devfn_t dev = PCI_DEV(0, 0x14, 3); |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 243 | |
| 244 | u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) |
| 245 | & 0xfffffff0; |
| 246 | if (!base){ |
| 247 | base = SPI_BASE_ADDRESS; |
| 248 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base |
| 249 | | SPI_ROM_ENABLE); |
| 250 | /* PCI_COMMAND_MEMORY is read-only and enabled. */ |
| 251 | } |
| 252 | return (uintptr_t)base; |
| 253 | } |
| 254 | |
| 255 | void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) |
| 256 | { |
| 257 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 258 | write16((void *)(base + SPI100_SPEED_CONFIG), |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 259 | (norm << SPI_NORM_SPEED_NEW_SH) | |
| 260 | (fast << SPI_FAST_SPEED_NEW_SH) | |
| 261 | (alt << SPI_ALT_SPEED_NEW_SH) | |
| 262 | (tpm << SPI_TPM_SPEED_NEW_SH)); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 263 | write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 264 | } |
| 265 | |
| 266 | void hudson_disable_4dw_burst(void) |
| 267 | { |
| 268 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 269 | write16((void *)(base + SPI100_HOST_PREF_CONFIG), |
| 270 | read16((void *)(base + SPI100_HOST_PREF_CONFIG)) |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 271 | & ~SPI_RD4DW_EN_HOST); |
| 272 | } |
| 273 | |
| 274 | /* Hudson 1-3 only. For Hudson 1, call with fast=1 */ |
| 275 | void hudson_set_readspeed(u16 norm, u16 fast) |
| 276 | { |
| 277 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 278 | write16((void *)(base + SPI_CNTRL1), |
| 279 | (read16((void *)(base + SPI_CNTRL1)) |
| 280 | & ~SPI_CNTRL1_SPEED_MASK) |
| 281 | | (norm << SPI_NORM_SPEED_SH) |
| 282 | | (fast << SPI_FAST_SPEED_SH)); |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | void hudson_read_mode(u32 mode) |
| 286 | { |
| 287 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 288 | write32((void *)(base + SPI_CNTRL0), |
| 289 | (read32((void *)(base + SPI_CNTRL0)) |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 290 | & ~SPI_READ_MODE_MASK) | mode); |
| 291 | } |
| 292 | |
Marc Jones | 6fcaaef | 2017-04-20 16:48:42 -0600 | [diff] [blame] | 293 | void hudson_tpm_decode_spi(void) |
| 294 | { |
Elyes HAOUAS | d9ef546 | 2018-05-19 17:08:23 +0200 | [diff] [blame] | 295 | pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */ |
Marc Jones | 6fcaaef | 2017-04-20 16:48:42 -0600 | [diff] [blame] | 296 | |
| 297 | u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); |
| 298 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase |
| 299 | | ROUTE_TPM_2_SPI); |
| 300 | } |
| 301 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 302 | #endif |