sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller
Location in hudson_lpc_port80() was called conditionally.
Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX()
due the change from IO to MMIO using pm_read/write.
Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 56b894c..0e3646b 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -22,6 +22,7 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <console/console.h>
+#include <amdblocks/acpimmio.h>
#include "hudson.h"
#include "pci_devs.h"
@@ -106,13 +107,6 @@
u8 byte;
pci_devfn_t dev;
- /* Enable LPC controller */
- outb(0xEC, 0xCD6);
- byte = inb(0xCD7);
- byte |= 1;
- outb(0xEC, 0xCD6);
- outb(byte, 0xCD7);
-
/* Enable port 80 LPC decode in pci function 3 configuration space. */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x4a);
@@ -125,6 +119,9 @@
pci_devfn_t dev;
u32 tmp;
+ /* Enable LPC controller */
+ pm_write8(0xec, pm_read8(0xec) | 0x01);
+
dev = PCI_DEV(0, 0x14, 3);
/* Serial port numeration on Hudson:
* PORT0 - 0x3f8