Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef _HUDSON_EARLY_SETUP_C_ |
| 17 | #define _HUDSON_EARLY_SETUP_C_ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <arch/acpi.h> |
| 22 | #include <console/console.h> |
| 23 | #include <reset.h> |
| 24 | #include <arch/cpu.h> |
| 25 | #include <cbmem.h> |
| 26 | #include "hudson.h" |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 27 | #include "pci_devs.h" |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 28 | |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame^] | 29 | #if IS_ENABLED(CONFIG_HUDSON_UART) |
| 30 | |
| 31 | #include <cpu/x86/msr.h> |
| 32 | #include <delay.h> |
| 33 | #include <Fch/Fch.h> |
| 34 | |
| 35 | void configure_hudson_uart(void) |
| 36 | { |
| 37 | msr_t msr; |
| 38 | u8 byte; |
| 39 | |
| 40 | msr = rdmsr(0x1B); |
| 41 | msr.lo |= 1 << 11; |
| 42 | wrmsr(0x1B, msr); |
| 43 | byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); |
| 44 | byte |= 1 << 3; |
| 45 | write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte); |
| 46 | byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62); |
| 47 | byte |= 1 << 3; |
| 48 | write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte); |
| 49 | write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); |
| 50 | write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); |
| 51 | write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); |
| 52 | write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); |
| 53 | |
| 54 | udelay(2000); |
| 55 | write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */ |
| 56 | } |
| 57 | |
| 58 | #endif |
| 59 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 60 | void hudson_pci_port80(void) |
| 61 | { |
| 62 | u8 byte; |
| 63 | device_t dev; |
| 64 | |
| 65 | /* P2P Bridge */ |
| 66 | dev = PCI_DEV(0, 0x14, 4); |
| 67 | |
| 68 | /* Chip Control: Enable subtractive decoding */ |
| 69 | byte = pci_read_config8(dev, 0x40); |
| 70 | byte |= 1 << 5; |
| 71 | pci_write_config8(dev, 0x40, byte); |
| 72 | |
| 73 | /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ |
| 74 | byte = pci_read_config8(dev, 0x4B); |
| 75 | byte |= 1 << 7; |
| 76 | pci_write_config8(dev, 0x4B, byte); |
| 77 | |
| 78 | /* The same IO Base and IO Limit here is meaningful because we set the |
| 79 | * bridge to be subtractive. During early setup stage, we have to make |
| 80 | * sure that data can go through port 0x80. |
| 81 | */ |
| 82 | /* IO Base: 0xf000 */ |
| 83 | byte = pci_read_config8(dev, 0x1C); |
| 84 | byte |= 0xF << 4; |
| 85 | pci_write_config8(dev, 0x1C, byte); |
| 86 | |
| 87 | /* IO Limit: 0xf000 */ |
| 88 | byte = pci_read_config8(dev, 0x1D); |
| 89 | byte |= 0xF << 4; |
| 90 | pci_write_config8(dev, 0x1D, byte); |
| 91 | |
| 92 | /* PCI Command: Enable IO response */ |
| 93 | byte = pci_read_config8(dev, 0x04); |
| 94 | byte |= 1 << 0; |
| 95 | pci_write_config8(dev, 0x04, byte); |
| 96 | |
| 97 | /* LPC controller */ |
| 98 | dev = PCI_DEV(0, 0x14, 3); |
| 99 | |
| 100 | byte = pci_read_config8(dev, 0x4A); |
| 101 | byte &= ~(1 << 5); /* disable lpc port 80 */ |
| 102 | pci_write_config8(dev, 0x4A, byte); |
| 103 | } |
| 104 | |
| 105 | void hudson_lpc_port80(void) |
| 106 | { |
| 107 | u8 byte; |
| 108 | device_t dev; |
| 109 | |
| 110 | /* Enable LPC controller */ |
| 111 | outb(0xEC, 0xCD6); |
| 112 | byte = inb(0xCD7); |
| 113 | byte |= 1; |
| 114 | outb(0xEC, 0xCD6); |
| 115 | outb(byte, 0xCD7); |
| 116 | |
| 117 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
| 118 | dev = PCI_DEV(0, 0x14, 3); |
| 119 | byte = pci_read_config8(dev, 0x4a); |
| 120 | byte |= 1 << 5; /* enable port 80 */ |
| 121 | pci_write_config8(dev, 0x4a, byte); |
| 122 | } |
| 123 | |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 124 | void hudson_lpc_decode(void) |
| 125 | { |
| 126 | device_t dev; |
| 127 | u32 tmp = 0; |
| 128 | |
| 129 | /* Enable I/O decode to LPC bus */ |
| 130 | dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); |
| 131 | tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 |
| 132 | | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 |
| 133 | | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 |
| 134 | | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 |
| 135 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 |
| 136 | | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 |
| 137 | | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 |
| 138 | | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 |
| 139 | | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 |
| 140 | | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT |
| 141 | | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT |
| 142 | | DECODE_ENABLE_ADLIB_PORT; |
| 143 | |
| 144 | pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); |
| 145 | } |
| 146 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 147 | int s3_save_nvram_early(u32 dword, int size, int nvram_pos) |
| 148 | { |
| 149 | int i; |
| 150 | printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); |
| 151 | |
| 152 | for (i = 0; i<size; i++) { |
| 153 | outb(nvram_pos, BIOSRAM_INDEX); |
| 154 | outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); |
| 155 | nvram_pos++; |
| 156 | } |
| 157 | |
| 158 | return nvram_pos; |
| 159 | } |
| 160 | |
| 161 | int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) |
| 162 | { |
| 163 | u32 data = *old_dword; |
| 164 | int i; |
| 165 | for (i = 0; i<size; i++) { |
| 166 | outb(nvram_pos, BIOSRAM_INDEX); |
| 167 | data &= ~(0xff << (i * 8)); |
| 168 | data |= inb(BIOSRAM_DATA) << (i *8); |
| 169 | nvram_pos++; |
| 170 | } |
| 171 | *old_dword = data; |
| 172 | printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, |
| 173 | nvram_pos-size); |
| 174 | return nvram_pos; |
| 175 | } |
| 176 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 177 | #endif |