southbridge/amd/pi: Enable early I/O decode to LPC
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.
Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 9500d0e..08697b9 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -28,6 +28,7 @@
#include <arch/cpu.h>
#include <cbmem.h>
#include "hudson.h"
+#include "pci_devs.h"
void hudson_pci_port80(void)
{
@@ -93,6 +94,29 @@
pci_write_config8(dev, 0x4a, byte);
}
+void hudson_lpc_decode(void)
+{
+ device_t dev;
+ u32 tmp = 0;
+
+ /* Enable I/O decode to LPC bus */
+ dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+ tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
+ | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
+ | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
+ | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
+ | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
+ | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
+ | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
+ | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
+ | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
+ | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
+ | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
+ | DECODE_ENABLE_ADLIB_PORT;
+
+ pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
+}
+
int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
{
int i;