Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef _HUDSON_EARLY_SETUP_C_ |
| 17 | #define _HUDSON_EARLY_SETUP_C_ |
| 18 | |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 19 | #include <assert.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame^] | 22 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 24 | #include <arch/acpi.h> |
| 25 | #include <console/console.h> |
| 26 | #include <reset.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 27 | #include "hudson.h" |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 28 | #include "pci_devs.h" |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 29 | #include <Fch/Fch.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 30 | |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 31 | #if IS_ENABLED(CONFIG_HUDSON_UART) |
| 32 | |
| 33 | #include <cpu/x86/msr.h> |
| 34 | #include <delay.h> |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 35 | |
| 36 | void configure_hudson_uart(void) |
| 37 | { |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 38 | u8 byte; |
| 39 | |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 40 | byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + |
Marshall Dawson | 500d81a | 2018-12-05 17:30:44 -0700 | [diff] [blame] | 41 | CONFIG_UART_FOR_CONSOLE * sizeof(u16))); |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 42 | byte |= 1 << 3; |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 43 | write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + |
Marshall Dawson | 500d81a | 2018-12-05 17:30:44 -0700 | [diff] [blame] | 44 | CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 45 | byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 46 | byte |= 1 << 3; |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 47 | write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 48 | write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); |
| 49 | write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); |
| 50 | write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); |
| 51 | write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); |
| 52 | |
| 53 | udelay(2000); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 54 | write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88), |
| 55 | 0x01); /* reset UART */ |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | #endif |
| 59 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 60 | void hudson_pci_port80(void) |
| 61 | { |
| 62 | u8 byte; |
Antonello Dettori | 1ac9728 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 63 | pci_devfn_t dev; |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 64 | |
| 65 | /* P2P Bridge */ |
| 66 | dev = PCI_DEV(0, 0x14, 4); |
| 67 | |
| 68 | /* Chip Control: Enable subtractive decoding */ |
| 69 | byte = pci_read_config8(dev, 0x40); |
| 70 | byte |= 1 << 5; |
| 71 | pci_write_config8(dev, 0x40, byte); |
| 72 | |
| 73 | /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ |
| 74 | byte = pci_read_config8(dev, 0x4B); |
| 75 | byte |= 1 << 7; |
| 76 | pci_write_config8(dev, 0x4B, byte); |
| 77 | |
| 78 | /* The same IO Base and IO Limit here is meaningful because we set the |
| 79 | * bridge to be subtractive. During early setup stage, we have to make |
| 80 | * sure that data can go through port 0x80. |
| 81 | */ |
| 82 | /* IO Base: 0xf000 */ |
| 83 | byte = pci_read_config8(dev, 0x1C); |
| 84 | byte |= 0xF << 4; |
| 85 | pci_write_config8(dev, 0x1C, byte); |
| 86 | |
| 87 | /* IO Limit: 0xf000 */ |
| 88 | byte = pci_read_config8(dev, 0x1D); |
| 89 | byte |= 0xF << 4; |
| 90 | pci_write_config8(dev, 0x1D, byte); |
| 91 | |
| 92 | /* PCI Command: Enable IO response */ |
| 93 | byte = pci_read_config8(dev, 0x04); |
| 94 | byte |= 1 << 0; |
| 95 | pci_write_config8(dev, 0x04, byte); |
| 96 | |
| 97 | /* LPC controller */ |
| 98 | dev = PCI_DEV(0, 0x14, 3); |
| 99 | |
| 100 | byte = pci_read_config8(dev, 0x4A); |
| 101 | byte &= ~(1 << 5); /* disable lpc port 80 */ |
| 102 | pci_write_config8(dev, 0x4A, byte); |
| 103 | } |
| 104 | |
| 105 | void hudson_lpc_port80(void) |
| 106 | { |
| 107 | u8 byte; |
Antonello Dettori | 1ac9728 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 108 | pci_devfn_t dev; |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 109 | |
| 110 | /* Enable LPC controller */ |
| 111 | outb(0xEC, 0xCD6); |
| 112 | byte = inb(0xCD7); |
| 113 | byte |= 1; |
| 114 | outb(0xEC, 0xCD6); |
| 115 | outb(byte, 0xCD7); |
| 116 | |
| 117 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
| 118 | dev = PCI_DEV(0, 0x14, 3); |
| 119 | byte = pci_read_config8(dev, 0x4a); |
| 120 | byte |= 1 << 5; /* enable port 80 */ |
| 121 | pci_write_config8(dev, 0x4a, byte); |
| 122 | } |
| 123 | |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 124 | void hudson_lpc_decode(void) |
| 125 | { |
Antonello Dettori | 1ac9728 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 126 | pci_devfn_t dev; |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 127 | u32 tmp = 0; |
| 128 | |
| 129 | /* Enable I/O decode to LPC bus */ |
| 130 | dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); |
| 131 | tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 |
| 132 | | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 |
| 133 | | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 |
| 134 | | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 |
| 135 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 |
| 136 | | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 |
| 137 | | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 |
| 138 | | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 |
| 139 | | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 |
| 140 | | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT |
| 141 | | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT |
| 142 | | DECODE_ENABLE_ADLIB_PORT; |
| 143 | |
| 144 | pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); |
| 145 | } |
| 146 | |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 147 | static void enable_wideio(uint8_t port, uint16_t size) |
| 148 | { |
| 149 | uint32_t wideio_enable[] = { |
| 150 | LPC_WIDEIO0_ENABLE, |
| 151 | LPC_WIDEIO1_ENABLE, |
| 152 | LPC_WIDEIO2_ENABLE |
| 153 | }; |
| 154 | uint32_t alt_wideio_enable[] = { |
| 155 | LPC_ALT_WIDEIO0_ENABLE, |
| 156 | LPC_ALT_WIDEIO1_ENABLE, |
| 157 | LPC_ALT_WIDEIO2_ENABLE |
| 158 | }; |
| 159 | pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); |
| 160 | uint32_t tmp; |
| 161 | |
| 162 | /* Only allow port 0-2 */ |
| 163 | assert(port <= ARRAY_SIZE(wideio_enable)); |
| 164 | |
| 165 | if (size == 16) { |
| 166 | tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 167 | tmp |= alt_wideio_enable[port]; |
| 168 | pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 169 | } else { /* 512 */ |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 170 | tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 171 | tmp &= ~alt_wideio_enable[port]; |
| 172 | pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); |
| 173 | } |
| 174 | |
| 175 | /* Enable the range */ |
| 176 | tmp = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 177 | tmp |= wideio_enable[port]; |
| 178 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * lpc_wideio_window() may be called any point in romstage, but take |
| 183 | * care that AGESA doesn't overwrite the range this function used. |
| 184 | * The function checks if there is an empty range and if all ranges are |
| 185 | * used the function throws an assert. The function doesn't check for a |
| 186 | * duplicate range, for ranges that can be merged into a single |
| 187 | * range, or ranges that overlap. |
| 188 | * |
| 189 | * The developer is expected to ensure that there are no conflicts. |
| 190 | */ |
| 191 | static void lpc_wideio_window(uint16_t base, uint16_t size) |
| 192 | { |
| 193 | pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); |
| 194 | u32 tmp; |
| 195 | |
| 196 | /* Support 512 or 16 bytes per range */ |
| 197 | assert(size == 512 || size == 16); |
| 198 | |
| 199 | /* Find and open Base Register and program it */ |
| 200 | tmp = pci_read_config32(dev, LPC_WIDEIO_GENERIC_PORT); |
| 201 | |
| 202 | if ((tmp & 0xFFFF) == 0) { /* WIDEIO0 */ |
| 203 | tmp |= base; |
| 204 | pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); |
| 205 | enable_wideio(0, size); |
| 206 | } else if ((tmp & 0xFFFF0000) == 0) { /* WIDEIO1 */ |
| 207 | tmp |= (base << 16); |
| 208 | pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); |
| 209 | enable_wideio(1, size); |
| 210 | } else { /* Check WIDEIO2 register */ |
| 211 | tmp = pci_read_config32(dev, LPC_WIDEIO2_GENERIC_PORT); |
| 212 | if ((tmp & 0xFFFF) == 0) { /* WIDEIO2 */ |
| 213 | tmp |= base; |
| 214 | pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp); |
| 215 | enable_wideio(2, size); |
| 216 | } else { /* All WIDEIO locations used*/ |
| 217 | assert(0); |
| 218 | } |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | void lpc_wideio_512_window(uint16_t base) |
| 223 | { |
| 224 | assert(IS_ALIGNED(base, 512)); |
| 225 | lpc_wideio_window(base, 512); |
| 226 | } |
| 227 | |
| 228 | void lpc_wideio_16_window(uint16_t base) |
| 229 | { |
| 230 | assert(IS_ALIGNED(base, 16)); |
| 231 | lpc_wideio_window(base, 16); |
| 232 | } |
| 233 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 234 | int s3_save_nvram_early(u32 dword, int size, int nvram_pos) |
| 235 | { |
| 236 | int i; |
| 237 | printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); |
| 238 | |
Elyes HAOUAS | c021ffe | 2016-09-18 19:18:56 +0200 | [diff] [blame] | 239 | for (i = 0; i < size; i++) { |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 240 | outb(nvram_pos, BIOSRAM_INDEX); |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 241 | outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 242 | nvram_pos++; |
| 243 | } |
| 244 | |
| 245 | return nvram_pos; |
| 246 | } |
| 247 | |
| 248 | int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) |
| 249 | { |
| 250 | u32 data = *old_dword; |
| 251 | int i; |
Elyes HAOUAS | c021ffe | 2016-09-18 19:18:56 +0200 | [diff] [blame] | 252 | for (i = 0; i < size; i++) { |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 253 | outb(nvram_pos, BIOSRAM_INDEX); |
| 254 | data &= ~(0xff << (i * 8)); |
| 255 | data |= inb(BIOSRAM_DATA) << (i *8); |
| 256 | nvram_pos++; |
| 257 | } |
| 258 | *old_dword = data; |
| 259 | printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, |
| 260 | nvram_pos-size); |
| 261 | return nvram_pos; |
| 262 | } |
| 263 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 264 | void hudson_clk_output_48Mhz(void) |
| 265 | { |
Marshall Dawson | 0bf3f55 | 2017-07-13 12:06:25 -0600 | [diff] [blame] | 266 | u32 ctrl; |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 267 | |
| 268 | /* |
| 269 | * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so |
| 270 | * 48Mhz will be on ball AP13 (FT3b package) |
| 271 | */ |
Marshall Dawson | 0bf3f55 | 2017-07-13 12:06:25 -0600 | [diff] [blame] | 272 | ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 273 | |
| 274 | /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ |
Marshall Dawson | 0bf3f55 | 2017-07-13 12:06:25 -0600 | [diff] [blame] | 275 | ctrl &= (u32)~(1<<2); |
| 276 | write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 277 | } |
| 278 | |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 279 | static uintptr_t hudson_spibase(void) |
| 280 | { |
| 281 | /* Make sure the base address is predictable */ |
Elyes HAOUAS | d9ef546 | 2018-05-19 17:08:23 +0200 | [diff] [blame] | 282 | pci_devfn_t dev = PCI_DEV(0, 0x14, 3); |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 283 | |
| 284 | u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) |
| 285 | & 0xfffffff0; |
| 286 | if (!base){ |
| 287 | base = SPI_BASE_ADDRESS; |
| 288 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base |
| 289 | | SPI_ROM_ENABLE); |
| 290 | /* PCI_COMMAND_MEMORY is read-only and enabled. */ |
| 291 | } |
| 292 | return (uintptr_t)base; |
| 293 | } |
| 294 | |
| 295 | void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) |
| 296 | { |
| 297 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 298 | write16((void *)(base + SPI100_SPEED_CONFIG), |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 299 | (norm << SPI_NORM_SPEED_NEW_SH) | |
| 300 | (fast << SPI_FAST_SPEED_NEW_SH) | |
| 301 | (alt << SPI_ALT_SPEED_NEW_SH) | |
| 302 | (tpm << SPI_TPM_SPEED_NEW_SH)); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 303 | write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | void hudson_disable_4dw_burst(void) |
| 307 | { |
| 308 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 309 | write16((void *)(base + SPI100_HOST_PREF_CONFIG), |
| 310 | read16((void *)(base + SPI100_HOST_PREF_CONFIG)) |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 311 | & ~SPI_RD4DW_EN_HOST); |
| 312 | } |
| 313 | |
| 314 | /* Hudson 1-3 only. For Hudson 1, call with fast=1 */ |
| 315 | void hudson_set_readspeed(u16 norm, u16 fast) |
| 316 | { |
| 317 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 318 | write16((void *)(base + SPI_CNTRL1), |
| 319 | (read16((void *)(base + SPI_CNTRL1)) |
| 320 | & ~SPI_CNTRL1_SPEED_MASK) |
| 321 | | (norm << SPI_NORM_SPEED_SH) |
| 322 | | (fast << SPI_FAST_SPEED_SH)); |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | void hudson_read_mode(u32 mode) |
| 326 | { |
| 327 | uintptr_t base = hudson_spibase(); |
Richard Spiegel | bd48b23 | 2018-11-02 08:25:00 -0700 | [diff] [blame] | 328 | write32((void *)(base + SPI_CNTRL0), |
| 329 | (read32((void *)(base + SPI_CNTRL0)) |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 330 | & ~SPI_READ_MODE_MASK) | mode); |
| 331 | } |
| 332 | |
Marc Jones | 6fcaaef | 2017-04-20 16:48:42 -0600 | [diff] [blame] | 333 | void hudson_tpm_decode_spi(void) |
| 334 | { |
Elyes HAOUAS | d9ef546 | 2018-05-19 17:08:23 +0200 | [diff] [blame] | 335 | pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */ |
Marc Jones | 6fcaaef | 2017-04-20 16:48:42 -0600 | [diff] [blame] | 336 | |
| 337 | u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); |
| 338 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase |
| 339 | | ROUTE_TPM_2_SPI); |
| 340 | } |
| 341 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 342 | #endif |