Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 2 | |
Srinidhi N Kaushik | 4af0adb | 2020-02-29 00:32:23 -0800 | [diff] [blame] | 3 | #include <assert.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 6 | #include <arch/pci_io_cfg.h> |
Subrata Banik | aec0716 | 2021-07-16 11:26:30 +0530 | [diff] [blame] | 7 | #include <cpu/intel/cpu_ids.h> |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 9 | #include <device/pci.h> |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 10 | #include <device/pci_ids.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 11 | #include <fsp/api.h> |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 12 | #include <fsp/ppi/mp_service_ppi.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 13 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 14 | #include <option.h> |
Jamie Ryu | 02a1b33 | 2020-06-11 01:57:13 -0700 | [diff] [blame] | 15 | #include <intelblocks/cse.h> |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 16 | #include <intelblocks/irq.h> |
Aamir Bohra | 86da00d | 2019-12-06 19:57:36 +0530 | [diff] [blame] | 17 | #include <intelblocks/lpss.h> |
Jamie Ryu | 5b7daa2 | 2020-08-18 18:54:49 -0700 | [diff] [blame] | 18 | #include <intelblocks/pmclib.h> |
Tim Wawrzynczak | eb6ebc0 | 2021-03-22 16:39:57 -0600 | [diff] [blame] | 19 | #include <intelblocks/tcss.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 20 | #include <intelblocks/xdci.h> |
Wonkyu Kim | 3ba64ca | 2020-03-20 12:17:14 -0700 | [diff] [blame] | 21 | #include <intelpch/lockdown.h> |
Jamie Ryu | 02a1b33 | 2020-06-11 01:57:13 -0700 | [diff] [blame] | 22 | #include <security/vboot/vboot_common.h> |
Jeremy Soller | 21d7c47 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 23 | #include <soc/gpio.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 24 | #include <soc/intel/common/vbt.h> |
Tim Wawrzynczak | 90f9cbb | 2021-07-19 16:07:42 -0600 | [diff] [blame] | 25 | #include <soc/lpm.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 27 | #include <soc/ramstage.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 28 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 29 | #include <soc/tcss.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 30 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 31 | #include <types.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 32 | |
Wonkyu Kim | 4cabf78 | 2020-05-20 13:09:39 -0700 | [diff] [blame] | 33 | /* THC assignment definition */ |
| 34 | #define THC_NONE 0 |
| 35 | #define THC_0 1 |
| 36 | #define THC_1 2 |
| 37 | |
Shaunak Saha | 1a8949c | 2020-06-08 18:59:47 -0700 | [diff] [blame] | 38 | /* SATA DEVSLP idle timeout default values */ |
| 39 | #define DEF_DMVAL 15 |
| 40 | #define DEF_DITOVAL 625 |
| 41 | |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 42 | /* |
Nick Vaccaro | 202b189 | 2021-02-22 14:26:13 -0800 | [diff] [blame] | 43 | * ME End of Post configuration |
| 44 | * 0 - Disable EOP. |
| 45 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 46 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 47 | */ |
| 48 | enum { |
Tim Wawrzynczak | 25d2452 | 2021-06-17 12:44:06 -0600 | [diff] [blame] | 49 | EOP_DISABLE = 0, |
| 50 | EOP_PEI = 1, |
| 51 | EOP_DXE = 2, |
| 52 | }; |
Nick Vaccaro | 202b189 | 2021-02-22 14:26:13 -0800 | [diff] [blame] | 53 | |
| 54 | /* |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 55 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 56 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 57 | * In order to ensure that mainboard setting does not disable L1 substates |
| 58 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 59 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 60 | * value is set in fsp_params. |
| 61 | * 0: Use FSP UPD default |
| 62 | * 1: Disable L1 substates |
| 63 | * 2: Use L1.1 |
| 64 | * 3: Use L1.2 (FSP UPD default) |
| 65 | */ |
| 66 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 67 | { |
| 68 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 69 | ctl = L1_SS_L1_2; |
| 70 | return ctl - 1; |
| 71 | } |
| 72 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 73 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 74 | { |
| 75 | const struct soc_intel_tigerlake_config *config; |
| 76 | config = config_of_soc(); |
| 77 | |
| 78 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| 79 | params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| 80 | |
| 81 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| 82 | params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 83 | params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 84 | params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| 85 | } |
| 86 | |
| 87 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| 88 | params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| 89 | } |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 90 | |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 91 | /* |
| 92 | * The FSP expects a certain list of PCI devices to be in the DevIntConfig table, |
| 93 | * regardless of whether or not they are used by the mainboard. |
| 94 | */ |
| 95 | static const struct slot_irq_constraints irq_constraints[] = { |
| 96 | { |
Tim Crawford | 5960978 | 2022-05-25 12:36:47 -0600 | [diff] [blame] | 97 | .slot = SA_DEV_SLOT_PEG, |
| 98 | .fns = { |
| 99 | FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_A, PIRQ_A), |
| 100 | FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_B, PIRQ_B), |
| 101 | FIXED_INT_PIRQ(SA_DEVFN_PEG3, PCI_INT_C, PIRQ_C), |
| 102 | }, |
| 103 | }, |
| 104 | { |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 105 | .slot = SA_DEV_SLOT_IGD, |
| 106 | .fns = { |
| 107 | ANY_PIRQ(SA_DEVFN_IGD), |
| 108 | }, |
| 109 | }, |
| 110 | { |
| 111 | .slot = SA_DEV_SLOT_DPTF, |
| 112 | .fns = { |
| 113 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 114 | }, |
| 115 | }, |
| 116 | { |
| 117 | .slot = SA_DEV_SLOT_IPU, |
| 118 | .fns = { |
| 119 | ANY_PIRQ(SA_DEVFN_IPU), |
| 120 | }, |
| 121 | }, |
| 122 | { |
| 123 | .slot = SA_DEV_SLOT_CPU_PCIE, |
| 124 | .fns = { |
| 125 | ANY_PIRQ(SA_DEVFN_CPU_PCIE), |
| 126 | }, |
| 127 | }, |
| 128 | { |
| 129 | .slot = SA_DEV_SLOT_TBT, |
| 130 | .fns = { |
| 131 | FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT0, PCI_INT_A), |
| 132 | FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT1, PCI_INT_B), |
| 133 | FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT2, PCI_INT_C), |
| 134 | FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT3, PCI_INT_D), |
| 135 | }, |
| 136 | }, |
| 137 | { |
| 138 | .slot = SA_DEV_SLOT_TCSS, |
| 139 | .fns = { |
| 140 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
| 141 | ANY_PIRQ(SA_DEVFN_TCSS_DMA0), |
| 142 | ANY_PIRQ(SA_DEVFN_TCSS_DMA1), |
| 143 | }, |
| 144 | }, |
| 145 | { |
| 146 | .slot = PCH_DEV_SLOT_SIO0, |
| 147 | .fns = { |
| 148 | ANY_PIRQ(PCH_DEVFN_THC0), |
| 149 | ANY_PIRQ(PCH_DEVFN_THC1), |
| 150 | }, |
| 151 | }, |
| 152 | { |
| 153 | .slot = PCH_DEV_SLOT_SIO1, |
| 154 | .fns = { |
| 155 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 156 | }, |
| 157 | }, |
| 158 | { |
| 159 | .slot = PCH_DEV_SLOT_ISH, |
| 160 | .fns = { |
| 161 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 162 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
| 163 | }, |
| 164 | }, |
| 165 | { |
| 166 | .slot = PCH_DEV_SLOT_SIO2, |
| 167 | .fns = { |
| 168 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 169 | }, |
| 170 | }, |
| 171 | { |
| 172 | .slot = PCH_DEV_SLOT_XHCI, |
| 173 | .fns = { |
| 174 | ANY_PIRQ(PCH_DEVFN_XHCI), |
Sean Rhodes | e8b6b07 | 2021-10-14 20:55:41 +0100 | [diff] [blame] | 175 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_CNVI_WIFI, PCI_INT_A), |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 176 | }, |
| 177 | }, |
| 178 | { |
| 179 | .slot = PCH_DEV_SLOT_SIO3, |
| 180 | .fns = { |
| 181 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 182 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 183 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 184 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 185 | }, |
| 186 | }, |
| 187 | { |
| 188 | .slot = PCH_DEV_SLOT_CSE, |
| 189 | .fns = { |
| 190 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 191 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 192 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 193 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 194 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 195 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 196 | }, |
| 197 | }, |
| 198 | { |
| 199 | .slot = PCH_DEV_SLOT_SATA, |
| 200 | .fns = { |
| 201 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 202 | }, |
| 203 | }, |
| 204 | { |
| 205 | .slot = PCH_DEV_SLOT_SIO4, |
| 206 | .fns = { |
| 207 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 208 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 209 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 210 | }, |
| 211 | }, |
| 212 | { |
| 213 | .slot = PCH_DEV_SLOT_PCIE, |
| 214 | .fns = { |
| 215 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 216 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 217 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 218 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 219 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 220 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 221 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 222 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 223 | }, |
| 224 | }, |
| 225 | { |
| 226 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 227 | .fns = { |
| 228 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 229 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 230 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 231 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 232 | }, |
| 233 | }, |
| 234 | { |
| 235 | .slot = PCH_DEV_SLOT_SIO5, |
| 236 | .fns = { |
| 237 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
| 238 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
| 239 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 240 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
| 241 | }, |
| 242 | }, |
| 243 | { |
| 244 | .slot = PCH_DEV_SLOT_ESPI, |
| 245 | .fns = { |
| 246 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 247 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 248 | ANY_PIRQ(PCH_DEVFN_GBE), |
| 249 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 250 | }, |
| 251 | }, |
| 252 | }; |
| 253 | |
Jes Klinke | 476ca3a | 2020-08-28 13:44:21 -0700 | [diff] [blame] | 254 | __weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) |
| 255 | { |
| 256 | /* Override settings per board. */ |
| 257 | } |
| 258 | |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 259 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 260 | { |
| 261 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 262 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 263 | size_t pch_total = 0; |
| 264 | size_t cfg_count = 0; |
| 265 | |
| 266 | if (!entry) |
| 267 | return NULL; |
| 268 | |
| 269 | /* Count PCH devices */ |
| 270 | while (entry) { |
| 271 | if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) |
| 272 | ++pch_total; |
| 273 | entry = entry->next; |
| 274 | } |
| 275 | |
| 276 | /* Convert PCH device entries to FSP format */ |
| 277 | config = calloc(pch_total, sizeof(*config)); |
| 278 | entry = get_cached_pci_irqs(); |
| 279 | while (entry) { |
| 280 | if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { |
| 281 | entry = entry->next; |
| 282 | continue; |
| 283 | } |
| 284 | |
| 285 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 286 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 287 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 288 | config[cfg_count].Irq = entry->irq; |
| 289 | ++cfg_count; |
| 290 | |
| 291 | entry = entry->next; |
| 292 | } |
| 293 | |
| 294 | *out_count = cfg_count; |
| 295 | |
| 296 | return config; |
| 297 | } |
| 298 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 299 | /* UPD parameters to be initialized before SiliconInit */ |
| 300 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 301 | { |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 302 | int i; |
John Zhao | bd615d6 | 2020-07-27 13:22:11 -0700 | [diff] [blame] | 303 | uint32_t cpu_id; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 304 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 305 | struct device *dev; |
| 306 | struct soc_intel_tigerlake_config *config; |
| 307 | config = config_of_soc(); |
Jes Klinke | 476ca3a | 2020-08-28 13:44:21 -0700 | [diff] [blame] | 308 | mainboard_update_soc_chip_config(config); |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 309 | |
| 310 | /* Parse device tree and enable/disable Serial I/O devices */ |
| 311 | parse_devicetree(params); |
| 312 | |
| 313 | /* Load VBT before devicetree-specific config. */ |
| 314 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 315 | |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 316 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | 49a2109 | 2021-06-09 03:58:25 +0530 | [diff] [blame] | 317 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 318 | |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 319 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
Subrata Banik | 6362de3 | 2020-07-30 11:31:55 +0530 | [diff] [blame] | 320 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 321 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 322 | |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 323 | /* D3Hot and D3Cold for TCSS */ |
John Zhao | bd615d6 | 2020-07-27 13:22:11 -0700 | [diff] [blame] | 324 | params->D3HotEnable = !config->TcssD3HotDisable; |
| 325 | cpu_id = cpu_get_cpuid(); |
| 326 | if (cpu_id == CPUID_TIGERLAKE_A0) |
| 327 | params->D3ColdEnable = 0; |
| 328 | else |
| 329 | params->D3ColdEnable = !config->TcssD3ColdDisable; |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 330 | |
Brandon Breitenstein | bf50c31 | 2020-12-21 14:55:38 -0800 | [diff] [blame] | 331 | params->UsbTcPortEn = config->UsbTcPortEn; |
Brandon Breitenstein | fc93237 | 2020-03-11 14:07:23 -0700 | [diff] [blame] | 332 | params->TcssAuxOri = config->TcssAuxOri; |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 333 | |
| 334 | /* Explicitly clear this field to avoid using defaults */ |
| 335 | memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg)); |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 336 | |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 337 | |
| 338 | /* Assign PCI IRQs */ |
| 339 | if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) |
| 340 | die("ERROR: Unable to assign PCI IRQs, and no ACPI _PRT table is defined\n"); |
| 341 | |
| 342 | size_t pch_count = 0; |
| 343 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 344 | params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 345 | params->NumOfDevIntConfig = pch_count; |
| 346 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 347 | |
John Zhao | 92a3a30 | 2020-06-03 13:06:24 -0700 | [diff] [blame] | 348 | /* |
| 349 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 350 | * evaluate this UPD value and skip sending command. There will be no |
| 351 | * delay for command completion. |
| 352 | */ |
| 353 | params->ITbtConnectTopologyTimeoutInMs = 0; |
| 354 | |
Srinidhi N Kaushik | 44509d8 | 2021-01-08 10:01:25 -0800 | [diff] [blame] | 355 | /* Disable TcColdOnUsbConnect */ |
| 356 | params->DisableTccoldOnUsbConnected = 1; |
| 357 | |
Wonkyu Kim | 3ba64ca | 2020-03-20 12:17:14 -0700 | [diff] [blame] | 358 | /* Chipset Lockdown */ |
Felix Singer | 673e6d1 | 2021-05-03 02:28:16 +0200 | [diff] [blame] | 359 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 360 | params->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 361 | params->PchLockDownBiosInterface = lockdown_by_fsp; |
| 362 | params->PchUnlockGpioPads = !lockdown_by_fsp; |
| 363 | params->RtcMemoryLock = lockdown_by_fsp; |
Tim Wawrzynczak | 5896608 | 2021-08-25 09:32:19 -0600 | [diff] [blame] | 364 | params->SkipPamLock = !lockdown_by_fsp; |
Wonkyu Kim | 3ba64ca | 2020-03-20 12:17:14 -0700 | [diff] [blame] | 365 | |
Tim Wawrzynczak | 25d2452 | 2021-06-17 12:44:06 -0600 | [diff] [blame] | 366 | /* coreboot will send EOP before loading payload */ |
| 367 | params->EndOfPostMessage = EOP_DISABLE; |
Nick Vaccaro | 202b189 | 2021-02-22 14:26:13 -0800 | [diff] [blame] | 368 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 369 | /* USB */ |
| 370 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 371 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 372 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 373 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 374 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 375 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 376 | |
| 377 | if (config->usb2_ports[i].enable) |
| 378 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 379 | else |
| 380 | params->Usb2OverCurrentPin[i] = 0xff; |
John Zhao | 4ead6b33 | 2021-01-01 14:19:36 -0800 | [diff] [blame] | 381 | |
| 382 | if (config->usb2_ports[i].type_c) |
| 383 | params->PortResetMessageEnable[i] = 1; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 387 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 388 | if (config->usb3_ports[i].enable) { |
| 389 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 390 | } else { |
| 391 | params->Usb3OverCurrentPin[i] = 0xff; |
| 392 | } |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 393 | if (config->usb3_ports[i].tx_de_emp) { |
| 394 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 395 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 396 | } |
| 397 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 398 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 399 | params->Usb3HsioTxDownscaleAmp[i] = |
| 400 | config->usb3_ports[i].tx_downscale_amp; |
| 401 | } |
| 402 | } |
| 403 | |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 404 | /* RP Configs */ |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 405 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 406 | params->PcieRpL1Substates[i] = |
| 407 | get_l1_substate_control(config->PcieRpL1Substates[i]); |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 408 | params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; |
| 409 | params->PcieRpAdvancedErrorReporting[i] = |
| 410 | config->PcieRpAdvancedErrorReporting[i]; |
Wonkyu Kim | c66c153 | 2020-05-27 13:34:04 -0700 | [diff] [blame] | 411 | params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; |
Duncan Laurie | 17e905ac | 2020-10-27 17:57:13 -0700 | [diff] [blame] | 412 | params->PciePtm[i] = config->PciePtm[i]; |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 413 | params->PcieRpSlotImplemented[i] = config->PcieRpSlotImplemented[i]; |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 414 | } |
Meera Ravindranath | 0d6cc22 | 2020-04-29 12:19:33 +0530 | [diff] [blame] | 415 | |
| 416 | /* Enable ClkReqDetect for enabled port */ |
| 417 | memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, |
| 418 | sizeof(config->PcieRpClkReqDetect)); |
| 419 | |
Nick Vaccaro | 4b3e06e | 2021-05-11 16:39:32 -0700 | [diff] [blame] | 420 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 421 | if (config->tcss_ports[i].enable) |
| 422 | params->CpuUsb3OverCurrentPin[i] = |
| 423 | config->tcss_ports[i].ocpin; |
| 424 | } |
| 425 | |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 426 | params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 427 | |
| 428 | /* PCH UART selection for FSP Debug */ |
| 429 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
Srinidhi N Kaushik | 4af0adb | 2020-02-29 00:32:23 -0800 | [diff] [blame] | 430 | ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 431 | params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 432 | |
Wonkyu Kim | 815d96a | 2020-01-21 21:51:19 -0800 | [diff] [blame] | 433 | /* SATA */ |
Subrata Banik | 49a2109 | 2021-06-09 03:58:25 +0530 | [diff] [blame] | 434 | params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 435 | if (params->SataEnable) { |
Wonkyu Kim | 815d96a | 2020-01-21 21:51:19 -0800 | [diff] [blame] | 436 | params->SataMode = config->SataMode; |
| 437 | params->SataSalpSupport = config->SataSalpSupport; |
| 438 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 439 | sizeof(params->SataPortsEnable)); |
| 440 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 441 | sizeof(params->SataPortsDevSlp)); |
| 442 | } |
| 443 | |
Jes Klinke | 6fd87ff | 2020-08-10 13:30:40 -0700 | [diff] [blame] | 444 | /* S0iX: Selectively enable individual sub-states, |
| 445 | * by default all are enabled. |
| 446 | * |
| 447 | * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, |
| 448 | * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4 |
| 449 | */ |
Tim Wawrzynczak | 90f9cbb | 2021-07-19 16:07:42 -0600 | [diff] [blame] | 450 | params->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(config); |
Jes Klinke | 6fd87ff | 2020-08-10 13:30:40 -0700 | [diff] [blame] | 451 | |
Shaunak Saha | 32b8a51 | 2020-03-31 22:56:13 -0700 | [diff] [blame] | 452 | /* |
| 453 | * Power Optimizer for DMI and SATA. |
| 454 | * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. |
| 455 | * Boards not needing the optimizers explicitly disables them by setting |
| 456 | * these disable variables to 1 in devicetree overrides. |
| 457 | */ |
| 458 | params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
| 459 | params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
| 460 | |
Shaunak Saha | 1a8949c | 2020-06-08 18:59:47 -0700 | [diff] [blame] | 461 | /* |
| 462 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 463 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 464 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 465 | * The default values can be changed from devicetree. |
| 466 | */ |
| 467 | for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
| 468 | if (config->SataPortsEnableDitoConfig[i]) { |
| 469 | if (config->SataPortsDmVal[i]) |
| 470 | params->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 471 | else |
| 472 | params->SataPortsDmVal[i] = DEF_DMVAL; |
| 473 | |
| 474 | if (config->SataPortsDitoVal[i]) |
| 475 | params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
| 476 | else |
| 477 | params->SataPortsDitoVal[i] = DEF_DITOVAL; |
| 478 | } |
| 479 | } |
| 480 | |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 481 | params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; |
Shaunak Saha | 82d5123 | 2021-02-17 23:26:43 -0800 | [diff] [blame] | 482 | params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; |
| 483 | params->SlowSlewRate[0] = config->SlowSlewRate; |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 484 | |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 485 | /* Enable TCPU for processor thermal control */ |
Felix Singer | 2aa1ff4 | 2021-12-05 03:13:37 +0100 | [diff] [blame] | 486 | params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 487 | |
Sumeet R Pawnikar | 6caa476 | 2020-06-18 16:50:58 +0530 | [diff] [blame] | 488 | /* Set TccActivationOffset */ |
| 489 | params->TccActivationOffset = config->tcc_offset; |
| 490 | |
Wonkyu Kim | b3fa6a0 | 2020-02-27 15:54:56 -0800 | [diff] [blame] | 491 | /* LAN */ |
Subrata Banik | 49a2109 | 2021-06-09 03:58:25 +0530 | [diff] [blame] | 492 | params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Wonkyu Kim | b3fa6a0 | 2020-02-27 15:54:56 -0800 | [diff] [blame] | 493 | |
Srinidhi N Kaushik | 8488853 | 2020-03-05 00:54:02 -0800 | [diff] [blame] | 494 | /* CNVi */ |
Subrata Banik | 49a2109 | 2021-06-09 03:58:25 +0530 | [diff] [blame] | 495 | params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
Cliff Huang | b34be4d | 2021-02-04 15:37:24 -0800 | [diff] [blame] | 496 | params->CnviBtCore = config->CnviBtCore; |
John Zhao | c16fc8a | 2020-09-21 13:10:11 -0700 | [diff] [blame] | 497 | params->CnviBtAudioOffload = config->CnviBtAudioOffload; |
Cliff Huang | b34be4d | 2021-02-04 15:37:24 -0800 | [diff] [blame] | 498 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
| 499 | assert(params->CnviMode || !params->CnviBtCore); |
| 500 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
| 501 | assert(params->CnviBtCore || !params->CnviBtAudioOffload); |
John Zhao | c16fc8a | 2020-09-21 13:10:11 -0700 | [diff] [blame] | 502 | |
Wonkyu Kim | 165efa1 | 2020-05-05 09:10:13 -0700 | [diff] [blame] | 503 | /* VMD */ |
Subrata Banik | 49a2109 | 2021-06-09 03:58:25 +0530 | [diff] [blame] | 504 | params->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Wonkyu Kim | 165efa1 | 2020-05-05 09:10:13 -0700 | [diff] [blame] | 505 | |
Wonkyu Kim | 4cabf78 | 2020-05-20 13:09:39 -0700 | [diff] [blame] | 506 | /* THC */ |
Subrata Banik | 49a2109 | 2021-06-09 03:58:25 +0530 | [diff] [blame] | 507 | params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 508 | params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Wonkyu Kim | 4cabf78 | 2020-05-20 13:09:39 -0700 | [diff] [blame] | 509 | |
Subrata Banik | 1bfd56cb | 2020-02-24 15:14:22 +0530 | [diff] [blame] | 510 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 511 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 512 | params->Enable8254ClockGating = !use_8254; |
| 513 | params->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | 1bfd56cb | 2020-02-24 15:14:22 +0530 | [diff] [blame] | 514 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 515 | /* |
| 516 | * Legacy PM ACPI Timer (and TCO Timer) |
| 517 | * This *must* be 1 in any case to keep FSP from |
| 518 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 519 | * 2) disabling the PM ACPI Timer. |
| 520 | * We handle both by ourself! |
| 521 | */ |
| 522 | params->EnableTcoTimer = 1; |
| 523 | |
Wonkyu Kim | 2b4ded0 | 2020-03-03 01:43:45 -0800 | [diff] [blame] | 524 | /* Enable Hybrid storage auto detection */ |
Jamie Ryu | 02a1b33 | 2020-06-11 01:57:13 -0700 | [diff] [blame] | 525 | if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite() |
| 526 | && vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) { |
| 527 | /* |
| 528 | * CSE Lite SKU does not support hybrid storage dynamic configuration |
| 529 | * in CSE RO boot, and FSP does not allow to send the strap override |
| 530 | * HECI commands if CSE is not in normal mode; hence, hybrid storage |
| 531 | * mode is disabled on CSE RO boot in recovery boot mode. |
| 532 | */ |
| 533 | printk(BIOS_INFO, "cse_lite: CSE RO boot. HybridStorageMode disabled\n"); |
| 534 | params->HybridStorageMode = 0; |
| 535 | } else { |
| 536 | params->HybridStorageMode = config->HybridStorageMode; |
| 537 | } |
Wonkyu Kim | 2b4ded0 | 2020-03-03 01:43:45 -0800 | [diff] [blame] | 538 | |
Brandon Breitenstein | 1163745 | 2020-02-06 14:20:57 -0800 | [diff] [blame] | 539 | /* USB4/TBT */ |
| 540 | for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { |
| 541 | dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); |
Felix Singer | f424c8b | 2021-12-10 23:23:42 +0100 | [diff] [blame] | 542 | params->ITbtPcieRootPortEn[i] = is_dev_enabled(dev); |
Brandon Breitenstein | 1163745 | 2020-02-06 14:20:57 -0800 | [diff] [blame] | 543 | } |
| 544 | |
Venkata Krishna Nimmagadda | e18f719 | 2020-05-15 00:13:40 -0700 | [diff] [blame] | 545 | /* PCH FIVR settings override */ |
| 546 | if (config->ext_fivr_settings.configure_ext_fivr) { |
| 547 | params->PchFivrExtV1p05RailEnabledStates = |
| 548 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 549 | |
| 550 | params->PchFivrExtV1p05RailSupportedVoltageStates = |
| 551 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 552 | |
| 553 | params->PchFivrExtVnnRailEnabledStates = |
| 554 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 555 | |
| 556 | params->PchFivrExtVnnRailSupportedVoltageStates = |
| 557 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 558 | |
| 559 | /* convert mV to number of 2.5 mV increments */ |
| 560 | params->PchFivrExtVnnRailSxVoltage = |
| 561 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10) / 25; |
| 562 | |
| 563 | params->PchFivrExtV1p05RailIccMaximum = |
| 564 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 565 | |
| 566 | } |
| 567 | |
Jamie Ryu | 5b7daa2 | 2020-08-18 18:54:49 -0700 | [diff] [blame] | 568 | /* Apply minimum assertion width settings if non-zero */ |
| 569 | if (config->PchPmSlpS3MinAssert) |
| 570 | params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; |
| 571 | if (config->PchPmSlpS4MinAssert) |
| 572 | params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert; |
| 573 | if (config->PchPmSlpSusMinAssert) |
| 574 | params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; |
| 575 | if (config->PchPmSlpAMinAssert) |
| 576 | params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; |
| 577 | |
| 578 | /* Set Power Cycle Duration */ |
| 579 | if (config->PchPmPwrCycDur) |
| 580 | params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert, |
| 581 | config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, |
| 582 | config->PchPmPwrCycDur); |
| 583 | |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 584 | /* Override EnableMultiPhaseSiliconInit prior calling MultiPhaseSiInit */ |
| 585 | params->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); |
Ravi Sarawadi | d83e24d | 2020-10-14 16:30:38 -0700 | [diff] [blame] | 586 | |
| 587 | /* Disable C1 C-state Demotion */ |
| 588 | params->C1StateAutoDemotion = 0; |
| 589 | |
Derek Huang | 8056187 | 2021-03-15 12:11:19 +0800 | [diff] [blame] | 590 | /* USB2 Phy Sus power gating setting override */ |
| 591 | params->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; |
| 592 | |
Tim Crawford | f3c4f29 | 2021-08-07 00:30:15 -0600 | [diff] [blame] | 593 | /* |
| 594 | * Prevent FSP from programming write-once subsystem IDs by providing |
| 595 | * a custom SSID table. Must have at least one entry for the FSP to |
| 596 | * use the table. |
| 597 | */ |
| 598 | struct svid_ssid_init_entry { |
| 599 | union { |
| 600 | struct { |
| 601 | uint64_t reg:12; /* Register offset */ |
| 602 | uint64_t function:3; |
| 603 | uint64_t device:5; |
| 604 | uint64_t bus:8; |
| 605 | uint64_t :4; |
| 606 | uint64_t segment:16; |
| 607 | uint64_t :16; |
| 608 | }; |
| 609 | uint64_t segbusdevfuncregister; |
| 610 | }; |
| 611 | struct { |
| 612 | uint16_t svid; |
| 613 | uint16_t ssid; |
| 614 | }; |
| 615 | uint32_t reserved; |
| 616 | }; |
| 617 | |
| 618 | /* |
| 619 | * The xHCI and HDA devices have RW/L rather than RW/O registers for |
| 620 | * subsystem IDs and so must be written before FspSiliconInit locks |
| 621 | * them with their default values. |
| 622 | */ |
| 623 | const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA }; |
| 624 | static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)]; |
| 625 | |
| 626 | for (i = 0; i < ARRAY_SIZE(devfn_table); i++) { |
| 627 | ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; |
| 628 | ssid_table[i].device = PCI_SLOT(devfn_table[i]); |
| 629 | ssid_table[i].function = PCI_FUNC(devfn_table[i]); |
| 630 | dev = pcidev_path_on_root(devfn_table[i]); |
| 631 | if (dev) { |
| 632 | ssid_table[i].svid = dev->subsystem_vendor; |
| 633 | ssid_table[i].ssid = dev->subsystem_device; |
| 634 | } |
| 635 | } |
| 636 | |
| 637 | params->SiSsidTablePtr = (uintptr_t)ssid_table; |
| 638 | params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table); |
| 639 | |
| 640 | /* |
| 641 | * Replace the default SVID:SSID value with the values specified in |
| 642 | * the devicetree for the root device. |
| 643 | */ |
| 644 | dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 645 | params->SiCustomizedSvid = dev->subsystem_vendor; |
| 646 | params->SiCustomizedSsid = dev->subsystem_device; |
| 647 | |
| 648 | /* Ensure FSP will program the registers */ |
| 649 | params->SiSkipSsidProgramming = 0; |
| 650 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 651 | mainboard_silicon_init_params(params); |
| 652 | } |
| 653 | |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 654 | /* |
| 655 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 656 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 657 | * Phase | FSP return point | Purpose |
| 658 | * ------- + ------------------------------------------------ + ------------------------------- |
| 659 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 660 | */ |
| 661 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 662 | { |
| 663 | switch (phase_index) { |
| 664 | case 1: |
| 665 | /* TCSS specific initialization here */ |
Brandon Breitenstein | 99b38a9 | 2019-12-19 23:12:58 -0800 | [diff] [blame] | 666 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 667 | __FILE__, __func__); |
Tim Wawrzynczak | eb6ebc0 | 2021-03-22 16:39:57 -0600 | [diff] [blame] | 668 | |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 669 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 670 | const config_t *config = config_of_soc(); |
| 671 | tcss_configure(config->typec_aux_bias_pads); |
| 672 | } |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 673 | break; |
| 674 | default: |
| 675 | break; |
| 676 | } |
| 677 | } |
| 678 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 679 | /* Mainboard GPIO Configuration */ |
| 680 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 681 | { |
| 682 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 683 | } |