commit | fc932374a2860addbdf00dc3bd141b556508b8f3 | [log] [tgz] |
---|---|---|
author | Brandon Breitenstein <brandon.breitenstein@intel.com> | Wed Mar 11 14:07:23 2020 -0700 |
committer | Patrick Georgi <pgeorgi@google.com> | Mon Mar 30 08:40:45 2020 +0000 |
tree | 3baf68b290d99f9cd580140475b0d0d70948eb5e | |
parent | bc8373830128ff2991c1a8e9ff3e4255deefe746 [diff] |
soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3 FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3. Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping. The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports. The TGL EDS describes this setting and what each bit represents. Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-C display should work regardless of Type-C cable orientation. Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.