Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 3 | |
Srinidhi N Kaushik | 4af0adb | 2020-02-29 00:32:23 -0800 | [diff] [blame] | 4 | #include <assert.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 8 | #include <fsp/api.h> |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 9 | #include <fsp/ppi/mp_service_ppi.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 10 | #include <fsp/util.h> |
Aamir Bohra | 86da00d | 2019-12-06 19:57:36 +0530 | [diff] [blame] | 11 | #include <intelblocks/lpss.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 12 | #include <intelblocks/xdci.h> |
Wonkyu Kim | 3ba64ca | 2020-03-20 12:17:14 -0700 | [diff] [blame] | 13 | #include <intelpch/lockdown.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 14 | #include <soc/gpio_soc_defs.h> |
| 15 | #include <soc/intel/common/vbt.h> |
| 16 | #include <soc/pci_devs.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 17 | #include <soc/ramstage.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 18 | #include <soc/soc_chip.h> |
| 19 | #include <string.h> |
| 20 | |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 21 | /* |
| 22 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 23 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 24 | * In order to ensure that mainboard setting does not disable L1 substates |
| 25 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 26 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 27 | * value is set in fsp_params. |
| 28 | * 0: Use FSP UPD default |
| 29 | * 1: Disable L1 substates |
| 30 | * 2: Use L1.1 |
| 31 | * 3: Use L1.2 (FSP UPD default) |
| 32 | */ |
| 33 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 34 | { |
| 35 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 36 | ctl = L1_SS_L1_2; |
| 37 | return ctl - 1; |
| 38 | } |
| 39 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 40 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 41 | { |
| 42 | const struct soc_intel_tigerlake_config *config; |
| 43 | config = config_of_soc(); |
| 44 | |
| 45 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| 46 | params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| 47 | |
| 48 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| 49 | params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 50 | params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 51 | params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| 52 | } |
| 53 | |
| 54 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| 55 | params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| 56 | } |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 57 | |
| 58 | static const pci_devfn_t serial_io_dev[] = { |
| 59 | PCH_DEVFN_I2C0, |
| 60 | PCH_DEVFN_I2C1, |
| 61 | PCH_DEVFN_I2C2, |
| 62 | PCH_DEVFN_I2C3, |
| 63 | PCH_DEVFN_I2C4, |
| 64 | PCH_DEVFN_I2C5, |
| 65 | PCH_DEVFN_GSPI0, |
| 66 | PCH_DEVFN_GSPI1, |
| 67 | PCH_DEVFN_GSPI2, |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 68 | PCH_DEVFN_GSPI3, |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 69 | PCH_DEVFN_UART0, |
| 70 | PCH_DEVFN_UART1, |
| 71 | PCH_DEVFN_UART2 |
| 72 | }; |
| 73 | |
| 74 | /* UPD parameters to be initialized before SiliconInit */ |
| 75 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 76 | { |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 77 | int i; |
| 78 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 79 | |
| 80 | struct device *dev; |
| 81 | struct soc_intel_tigerlake_config *config; |
| 82 | config = config_of_soc(); |
| 83 | |
| 84 | /* Parse device tree and enable/disable Serial I/O devices */ |
| 85 | parse_devicetree(params); |
| 86 | |
| 87 | /* Load VBT before devicetree-specific config. */ |
| 88 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 89 | |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 90 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 91 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 92 | if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) |
| 93 | params->PeiGraphicsPeimInit = 1; |
| 94 | else |
| 95 | params->PeiGraphicsPeimInit = 0; |
| 96 | |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 97 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 98 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { |
| 99 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 100 | params->SkipMpInit = 0; |
| 101 | } else { |
| 102 | params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; |
| 103 | } |
| 104 | |
Brandon Breitenstein | fc93237 | 2020-03-11 14:07:23 -0700 | [diff] [blame] | 105 | params->TcssAuxOri = config->TcssAuxOri; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 106 | for (i = 0; i < 8; i++) |
| 107 | params->IomTypeCPortPadCfg[i] = 0x09000000; |
| 108 | |
Wonkyu Kim | 3ba64ca | 2020-03-20 12:17:14 -0700 | [diff] [blame] | 109 | /* Chipset Lockdown */ |
| 110 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
| 111 | params->PchLockDownGlobalSmi = 0; |
| 112 | params->PchLockDownBiosInterface = 0; |
| 113 | params->PchUnlockGpioPads = 1; |
| 114 | params->RtcMemoryLock = 0; |
| 115 | } else { |
| 116 | params->PchLockDownGlobalSmi = 1; |
| 117 | params->PchLockDownBiosInterface = 1; |
| 118 | params->PchUnlockGpioPads = 0; |
| 119 | params->RtcMemoryLock = 1; |
| 120 | } |
| 121 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 122 | /* USB */ |
| 123 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 124 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 125 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 126 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 127 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 128 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 129 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 130 | } |
| 131 | |
| 132 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 133 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 134 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 135 | if (config->usb3_ports[i].tx_de_emp) { |
| 136 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 137 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 138 | } |
| 139 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 140 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 141 | params->Usb3HsioTxDownscaleAmp[i] = |
| 142 | config->usb3_ports[i].tx_downscale_amp; |
| 143 | } |
| 144 | } |
| 145 | |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 146 | /* RP Configs */ |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 147 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 148 | params->PcieRpL1Substates[i] = |
| 149 | get_l1_substate_control(config->PcieRpL1Substates[i]); |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 150 | params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; |
| 151 | params->PcieRpAdvancedErrorReporting[i] = |
| 152 | config->PcieRpAdvancedErrorReporting[i]; |
| 153 | } |
Meera Ravindranath | 0d6cc22 | 2020-04-29 12:19:33 +0530 | [diff] [blame^] | 154 | |
| 155 | /* Enable ClkReqDetect for enabled port */ |
| 156 | memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, |
| 157 | sizeof(config->PcieRpClkReqDetect)); |
| 158 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 159 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 160 | dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); |
John Zhao | ad64781 | 2020-03-03 10:03:57 -0800 | [diff] [blame] | 161 | if (dev) { |
| 162 | if (!xdci_can_enable()) |
| 163 | dev->enabled = 0; |
| 164 | params->XdciEnable = dev->enabled; |
| 165 | } else { |
| 166 | params->XdciEnable = 0; |
| 167 | } |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 168 | |
| 169 | /* PCH UART selection for FSP Debug */ |
| 170 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
Srinidhi N Kaushik | 4af0adb | 2020-02-29 00:32:23 -0800 | [diff] [blame] | 171 | ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 172 | params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 173 | |
Wonkyu Kim | 815d96a | 2020-01-21 21:51:19 -0800 | [diff] [blame] | 174 | /* SATA */ |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 175 | dev = pcidev_path_on_root(PCH_DEVFN_SATA); |
Wonkyu Kim | 815d96a | 2020-01-21 21:51:19 -0800 | [diff] [blame] | 176 | if (!dev) |
| 177 | params->SataEnable = 0; |
| 178 | else { |
| 179 | params->SataEnable = dev->enabled; |
| 180 | params->SataMode = config->SataMode; |
| 181 | params->SataSalpSupport = config->SataSalpSupport; |
| 182 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 183 | sizeof(params->SataPortsEnable)); |
| 184 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 185 | sizeof(params->SataPortsDevSlp)); |
| 186 | } |
| 187 | |
Wonkyu Kim | b3fa6a0 | 2020-02-27 15:54:56 -0800 | [diff] [blame] | 188 | /* LAN */ |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 189 | dev = pcidev_path_on_root(PCH_DEVFN_GBE); |
Wonkyu Kim | b3fa6a0 | 2020-02-27 15:54:56 -0800 | [diff] [blame] | 190 | if (!dev) |
| 191 | params->PchLanEnable = 0; |
| 192 | else |
| 193 | params->PchLanEnable = dev->enabled; |
| 194 | |
Srinidhi N Kaushik | 8488853 | 2020-03-05 00:54:02 -0800 | [diff] [blame] | 195 | /* CNVi */ |
Srinidhi N Kaushik | a6bff2d | 2020-03-12 01:15:43 -0700 | [diff] [blame] | 196 | dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); |
| 197 | if (dev) |
| 198 | params->CnviMode = dev->enabled; |
| 199 | else |
| 200 | params->CnviMode = 0; |
Srinidhi N Kaushik | 8488853 | 2020-03-05 00:54:02 -0800 | [diff] [blame] | 201 | |
Subrata Banik | 1bfd56cb | 2020-02-24 15:14:22 +0530 | [diff] [blame] | 202 | /* Legacy 8254 timer support */ |
| 203 | params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; |
| 204 | params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; |
| 205 | |
Wonkyu Kim | 2b4ded0 | 2020-03-03 01:43:45 -0800 | [diff] [blame] | 206 | /* Enable Hybrid storage auto detection */ |
| 207 | params->HybridStorageMode = config->HybridStorageMode; |
| 208 | |
Brandon Breitenstein | 1163745 | 2020-02-06 14:20:57 -0800 | [diff] [blame] | 209 | /* USB4/TBT */ |
| 210 | for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { |
| 211 | dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); |
| 212 | if (dev) |
| 213 | params->ITbtPcieRootPortEn[i] = dev->enabled; |
| 214 | else |
| 215 | params->ITbtPcieRootPortEn[i] = 0; |
| 216 | } |
| 217 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 218 | mainboard_silicon_init_params(params); |
| 219 | } |
| 220 | |
| 221 | /* Mainboard GPIO Configuration */ |
| 222 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 223 | { |
| 224 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | /* Return list of SOC LPSS controllers */ |
| 228 | const pci_devfn_t *soc_lpss_controllers_list(size_t *size) |
| 229 | { |
| 230 | *size = ARRAY_SIZE(serial_io_dev); |
| 231 | return serial_io_dev; |
| 232 | } |