Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2019 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame^] | 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 19 | #include <fsp/api.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame^] | 20 | #include <fsp/util.h> |
Aamir Bohra | 86da00d | 2019-12-06 19:57:36 +0530 | [diff] [blame] | 21 | #include <intelblocks/lpss.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame^] | 22 | #include <intelblocks/xdci.h> |
| 23 | #include <soc/gpio_soc_defs.h> |
| 24 | #include <soc/intel/common/vbt.h> |
| 25 | #include <soc/pci_devs.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 26 | #include <soc/ramstage.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame^] | 27 | #include <soc/soc_chip.h> |
| 28 | #include <string.h> |
| 29 | |
| 30 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 31 | { |
| 32 | const struct soc_intel_tigerlake_config *config; |
| 33 | config = config_of_soc(); |
| 34 | |
| 35 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| 36 | params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| 37 | |
| 38 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| 39 | params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 40 | params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 41 | params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| 42 | } |
| 43 | |
| 44 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| 45 | params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| 46 | } |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 47 | |
| 48 | static const pci_devfn_t serial_io_dev[] = { |
| 49 | PCH_DEVFN_I2C0, |
| 50 | PCH_DEVFN_I2C1, |
| 51 | PCH_DEVFN_I2C2, |
| 52 | PCH_DEVFN_I2C3, |
| 53 | PCH_DEVFN_I2C4, |
| 54 | PCH_DEVFN_I2C5, |
| 55 | PCH_DEVFN_GSPI0, |
| 56 | PCH_DEVFN_GSPI1, |
| 57 | PCH_DEVFN_GSPI2, |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame^] | 58 | PCH_DEVFN_GSPI3, |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 59 | PCH_DEVFN_UART0, |
| 60 | PCH_DEVFN_UART1, |
| 61 | PCH_DEVFN_UART2 |
| 62 | }; |
| 63 | |
| 64 | /* UPD parameters to be initialized before SiliconInit */ |
| 65 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 66 | { |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame^] | 67 | int i; |
| 68 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 69 | |
| 70 | struct device *dev; |
| 71 | struct soc_intel_tigerlake_config *config; |
| 72 | config = config_of_soc(); |
| 73 | |
| 74 | /* Parse device tree and enable/disable Serial I/O devices */ |
| 75 | parse_devicetree(params); |
| 76 | |
| 77 | /* Load VBT before devicetree-specific config. */ |
| 78 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 79 | |
| 80 | params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; |
| 81 | |
| 82 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 83 | if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) |
| 84 | params->PeiGraphicsPeimInit = 1; |
| 85 | else |
| 86 | params->PeiGraphicsPeimInit = 0; |
| 87 | |
| 88 | for (i = 0; i < 8; i++) |
| 89 | params->IomTypeCPortPadCfg[i] = 0x09000000; |
| 90 | |
| 91 | /* USB */ |
| 92 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 93 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 94 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 95 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 96 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 97 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 98 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 99 | } |
| 100 | |
| 101 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 102 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 103 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 104 | if (config->usb3_ports[i].tx_de_emp) { |
| 105 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 106 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 107 | } |
| 108 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 109 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 110 | params->Usb3HsioTxDownscaleAmp[i] = |
| 111 | config->usb3_ports[i].tx_downscale_amp; |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 116 | dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); |
| 117 | if (!xdci_can_enable()) |
| 118 | dev->enabled = 0; |
| 119 | params->XdciEnable = dev->enabled; |
| 120 | |
| 121 | /* PCH UART selection for FSP Debug */ |
| 122 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 123 | |
| 124 | mainboard_silicon_init_params(params); |
| 125 | } |
| 126 | |
| 127 | /* Mainboard GPIO Configuration */ |
| 128 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 129 | { |
| 130 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | /* Return list of SOC LPSS controllers */ |
| 134 | const pci_devfn_t *soc_lpss_controllers_list(size_t *size) |
| 135 | { |
| 136 | *size = ARRAY_SIZE(serial_io_dev); |
| 137 | return serial_io_dev; |
| 138 | } |