Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Matt DeVillier | 338c8d4 | 2018-07-16 20:29:10 -0500 | [diff] [blame] | 3 | # IGD Displays |
| 4 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 5 | |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 6 | register "panel_cfg" = "{ |
| 7 | .up_delay_ms = 200, |
| 8 | .down_delay_ms = 50, |
| 9 | .cycle_delay_ms = 500, |
| 10 | .backlight_on_delay_ms = 1, |
| 11 | .backlight_off_delay_ms = 200, |
| 12 | .backlight_pwm_hz = 1000, |
| 13 | }" |
Nico Huber | 55c5777 | 2018-12-16 03:39:35 +0100 | [diff] [blame] | 14 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 15 | # Enable deep Sx states |
| 16 | register "deep_s3_enable_ac" = "0" |
| 17 | register "deep_s3_enable_dc" = "0" |
| 18 | register "deep_s5_enable_ac" = "1" |
| 19 | register "deep_s5_enable_dc" = "1" |
| 20 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 21 | |
| 22 | # GPE configuration |
| 23 | # Note that GPE events called out in ASL code rely on this |
| 24 | # route. i.e. If this route changes then the affected GPE |
| 25 | # offset bits also need to be changed. |
| 26 | register "gpe0_dw0" = "GPP_B" |
| 27 | register "gpe0_dw1" = "GPP_D" |
| 28 | register "gpe0_dw2" = "GPP_E" |
| 29 | |
| 30 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 31 | register "gen1_dec" = "0x00fc0801" |
| 32 | register "gen2_dec" = "0x000c0201" |
| 33 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 34 | # Enable DPTF |
| 35 | register "dptf_enable" = "1" |
| 36 | |
| 37 | # FSP Configuration |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 38 | register "SataSalpSupport" = "0" |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 39 | register "SataPortsEnable[0]" = "0" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 40 | register "DspEnable" = "1" |
| 41 | register "IoBufferOwnership" = "3" |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 42 | register "SsicPortEnable" = "0" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 43 | register "ScsEmmcHs400Enabled" = "1" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 44 | register "SkipExtGfxScan" = "1" |
Angel Pons | 6fadde0 | 2021-04-04 16:11:53 +0200 | [diff] [blame] | 45 | register "SaGv" = "SaGv_Enabled" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 46 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 47 | register "PmConfigSlpS4MinAssert" = "4" # 4s |
| 48 | register "PmConfigSlpSusMinAssert" = "3" # 4s |
| 49 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 50 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 51 | # Enable Root port 1 |
| 52 | register "PcieRpEnable[0]" = "1" |
| 53 | # Enable CLKREQ# |
| 54 | register "PcieRpClkReqSupport[0]" = "1" |
| 55 | # RP 1 uses SRCCLKREQ1# |
| 56 | register "PcieRpClkReqNumber[0]" = "1" |
| 57 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 58 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 59 | register "SerialIoDevMode" = "{ |
| 60 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 61 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 62 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 63 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 64 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 65 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 66 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 67 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 68 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 69 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 70 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 71 | }" |
| 72 | |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 73 | # I2C4 is 1.8V |
| 74 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
| 75 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 76 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 77 | register "power_limits_config" = "{ |
| 78 | .tdp_pl2_override = 25, |
| 79 | }" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 80 | |
| 81 | # Send an extra VR mailbox command for the PS4 exit issue |
| 82 | register "SendVrMbxCmd" = "2" |
| 83 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 84 | device cpu_cluster 0 on end |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 85 | device domain 0 on |
Felix Singer | 3b3ac15 | 2023-11-12 19:05:03 +0000 | [diff] [blame] | 86 | device ref igpu on end |
| 87 | device ref sa_thermal on end |
| 88 | device ref south_xhci on end |
| 89 | device ref thermal on end |
| 90 | device ref i2c0 on end |
| 91 | device ref i2c1 on end |
| 92 | device ref heci1 on end |
| 93 | device ref uart2 on end |
| 94 | device ref i2c4 on end |
| 95 | device ref pcie_rp1 on |
Furquan Shaikh | a266d1e | 2020-10-04 12:52:54 -0700 | [diff] [blame] | 96 | chip drivers/wifi/generic |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 97 | register "wake" = "GPE0_DW0_16" |
| 98 | device pci 00.0 on end |
| 99 | end |
Felix Singer | 3b3ac15 | 2023-11-12 19:05:03 +0000 | [diff] [blame] | 100 | end |
| 101 | device ref uart0 on end |
| 102 | device ref emmc on end |
| 103 | device ref lpc_espi on |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 104 | chip drivers/pc80/tpm |
| 105 | device pnp 0c31.0 on end |
| 106 | end |
| 107 | chip ec/google/chromeec |
| 108 | device pnp 0c09.0 on end |
| 109 | end |
Felix Singer | 3b3ac15 | 2023-11-12 19:05:03 +0000 | [diff] [blame] | 110 | end |
| 111 | device ref hda on end |
| 112 | device ref smbus on end |
| 113 | device ref fast_spi on end |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 114 | end |
| 115 | end |