blob: 1b59fcc1b9da944513471dd2017b121415abc6a1 [file] [log] [blame]
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +00001chip northbridge/intel/i945
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01002 # IGD Displays
Nico Huberb0b25c82020-03-21 20:35:12 +01003 register "gfx" = "GMA_STATIC_DISPLAYS(0)"
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01004
Edward O'Callaghan61113de2014-05-18 10:33:31 +10005 device cpu_cluster 0 on
Arthur Heymans22d6ee82022-11-07 10:03:40 +01006 ops i945_cpu_bus_ops
Nico Huber4829af12019-02-27 14:23:18 +01007 chip cpu/intel/socket_m
Edward O'Callaghan61113de2014-05-18 10:33:31 +10008 device lapic 0 on end
9 end
10 end
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000011
Arthur Heymans885c2892016-10-03 17:16:48 +020012 register "pci_mmio_size" = "768"
13
Edward O'Callaghan61113de2014-05-18 10:33:31 +100014 device domain 0 on
Arthur Heymans22d6ee82022-11-07 10:03:40 +010015 ops i945_pci_domain_ops
Edward O'Callaghan61113de2014-05-18 10:33:31 +100016 device pci 00.0 on end # host bridge
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000017 device pci 01.0 off end # i945 PCIe root port
18 device pci 02.0 on end # vga controller
19 device pci 02.1 on end # display controller
20
Edward O'Callaghan61113de2014-05-18 10:33:31 +100021 chip southbridge/intel/i82801gx
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000022 register "pirqa_routing" = "0x05"
23 register "pirqb_routing" = "0x07"
24 register "pirqc_routing" = "0x05"
25 register "pirqd_routing" = "0x07"
26 register "pirqe_routing" = "0x80"
27 register "pirqf_routing" = "0x80"
28 register "pirqg_routing" = "0x80"
29 register "pirqh_routing" = "0x06"
30
31 # GPI routing
32 # 0 No effect (default)
33 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
34 # 2 SCI (if corresponding GPIO_EN bit is also set)
35 register "gpi13_routing" = "1"
36
Edward O'Callaghan61113de2014-05-18 10:33:31 +100037 register "ide_enable_primary" = "0x1"
38 register "ide_enable_secondary" = "0x0"
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000039
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +020040 register "c3_latency" = "85"
41 register "p_cnt_throttling_supported" = "0"
42
Arthur Heymansfecf7772019-11-09 14:19:04 +010043 register "gen1_dec" = "0x00fc0291"
44 register "gen4_dec" = "0x00000301"
45
Edward O'Callaghan61113de2014-05-18 10:33:31 +100046 #device pci 1b.0 on end # High Definition Audio
47 device pci 1c.0 on end # PCIe
48 device pci 1c.1 on end # PCIe
49 device pci 1c.2 on end # PCIe
Arthur Heymansb9d25892018-06-15 22:02:28 +020050 device pci 1c.3 on end # PCIe port 4
51 device pci 1c.4 on end # PCIe port 5
52 device pci 1c.5 on end # PCIe port 6
Edward O'Callaghan61113de2014-05-18 10:33:31 +100053 device pci 1d.0 on end # USB UHCI
54 device pci 1d.1 on end # USB UHCI
55 device pci 1d.2 on end # USB UHCI
56 device pci 1d.3 on end # USB UHCI
57 device pci 1d.7 on end # USB2 EHCI
58 device pci 1e.0 on end # PCI bridge
Arthur Heymansb9d25892018-06-15 22:02:28 +020059 device pci 1e.2 on end # AC'97 Audio
60 device pci 1e.3 on end # AC'97 Modem
Edward O'Callaghan61113de2014-05-18 10:33:31 +100061 device pci 1f.0 on # LPC bridge
62 chip superio/winbond/w83627ehg
63 device pnp 4e.0 off end # Floppy
64 device pnp 4e.1 off end # Parport
65 device pnp 4e.2 on # COM1
66 io 0x60 = 0x3f8
67 irq 0x70 = 4
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000068 end
Edward O'Callaghan61113de2014-05-18 10:33:31 +100069 device pnp 4e.3 on # COM2
70 io 0x60 = 0x2f8
71 irq 0x70 = 3
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000072 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
Edward O'Callaghan61113de2014-05-18 10:33:31 +100073 end
Uwe Hermann3a4ed152010-12-05 22:36:14 +000074 device pnp 4e.5 on # PS/2 keyboard & mouse
Edward O'Callaghan61113de2014-05-18 10:33:31 +100075 io 0x60 = 0x60
76 io 0x62 = 0x64
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000077 irq 0x70 = 1
78 irq 0x72 = 12
79 irq 0xf0 = 0x82 # HW accel A20.
80 end
Uwe Hermann3a4ed152010-12-05 22:36:14 +000081 device pnp 4e.106 off end # Serial flash interface (SFI)
82 device pnp 4e.007 off end # GPIO 1
83 device pnp 4e.107 off end # Game port
84 device pnp 4e.207 on # MIDI
85 io 0x62 = 0x330
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000086 irq 0x70 = 9
87 end
Uwe Hermann3a4ed152010-12-05 22:36:14 +000088 device pnp 4e.307 off end # GPIO 6
89 device pnp 4e.8 off end # WDTO#, PLED
90 device pnp 4e.009 on # GPIO 2
91 # All default
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000092 end
Uwe Hermann3a4ed152010-12-05 22:36:14 +000093 device pnp 4e.109 on # GPIO 3
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +000094 irq 0xf0 = 0xfb # set inputs/outputs
95 irq 0xf1 = 0x66
96 end
Uwe Hermann3a4ed152010-12-05 22:36:14 +000097 device pnp 4e.209 on # GPIO 4
98 end
99 device pnp 4e.309 off # GPIO 5
100 end
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000101 device pnp 4e.a on # ACPI
Uwe Hermann3a4ed152010-12-05 22:36:14 +0000102 # TODO: IRQ
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000103 end
104 device pnp 4e.b on # HWM
Uwe Hermann3a4ed152010-12-05 22:36:14 +0000105 io 0x60 = 0x290
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000106 irq 0x70 = 0
107 end
Edward O'Callaghan61113de2014-05-18 10:33:31 +1000108 end # chip superio/winbond/w83627ehg
109 end # LPC bridge
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000110 device pci 1f.1 on end # IDE
Edward O'Callaghan61113de2014-05-18 10:33:31 +1000111 device pci 1f.2 on end # SATA
112 device pci 1f.3 on end # SMBus
Edward O'Callaghan61113de2014-05-18 10:33:31 +1000113 end # chip southbridge/intel/i82801gx
114
115 end # device domain0
116end # chip northbridge/intel/i945