Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
| 6 | #include <cpu/x86/mtrr.h> |
| 7 | #include <cpu/x86/msr.h> |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 8 | #include <cpu/x86/mp.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include <cpu/intel/microcode.h> |
Kyösti Mälkki | faf20d3 | 2019-08-14 05:41:41 +0300 | [diff] [blame] | 10 | #include <cpu/intel/smm_reloc.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 11 | #include <cpu/intel/speedstep.h> |
| 12 | #include <cpu/intel/turbo.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | #include <cpu/x86/name.h> |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 14 | #include <delay.h> |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 15 | #include <northbridge/intel/haswell/haswell.h> |
| 16 | #include <southbridge/intel/lynxpoint/pch.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 17 | #include <cpu/intel/common/common.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 18 | #include <types.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | #include "haswell.h" |
| 20 | #include "chip.h" |
| 21 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 23 | static const u8 power_limit_time_sec_to_msr[] = { |
| 24 | [0] = 0x00, |
| 25 | [1] = 0x0a, |
| 26 | [2] = 0x0b, |
| 27 | [3] = 0x4b, |
| 28 | [4] = 0x0c, |
| 29 | [5] = 0x2c, |
| 30 | [6] = 0x4c, |
| 31 | [7] = 0x6c, |
| 32 | [8] = 0x0d, |
| 33 | [10] = 0x2d, |
| 34 | [12] = 0x4d, |
| 35 | [14] = 0x6d, |
| 36 | [16] = 0x0e, |
| 37 | [20] = 0x2e, |
| 38 | [24] = 0x4e, |
| 39 | [28] = 0x6e, |
| 40 | [32] = 0x0f, |
| 41 | [40] = 0x2f, |
| 42 | [48] = 0x4f, |
| 43 | [56] = 0x6f, |
| 44 | [64] = 0x10, |
| 45 | [80] = 0x30, |
| 46 | [96] = 0x50, |
| 47 | [112] = 0x70, |
| 48 | [128] = 0x11, |
| 49 | }; |
| 50 | |
| 51 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 52 | static const u8 power_limit_time_msr_to_sec[] = { |
| 53 | [0x00] = 0, |
| 54 | [0x0a] = 1, |
| 55 | [0x0b] = 2, |
| 56 | [0x4b] = 3, |
| 57 | [0x0c] = 4, |
| 58 | [0x2c] = 5, |
| 59 | [0x4c] = 6, |
| 60 | [0x6c] = 7, |
| 61 | [0x0d] = 8, |
| 62 | [0x2d] = 10, |
| 63 | [0x4d] = 12, |
| 64 | [0x6d] = 14, |
| 65 | [0x0e] = 16, |
| 66 | [0x2e] = 20, |
| 67 | [0x4e] = 24, |
| 68 | [0x6e] = 28, |
| 69 | [0x0f] = 32, |
| 70 | [0x2f] = 40, |
| 71 | [0x4f] = 48, |
| 72 | [0x6f] = 56, |
| 73 | [0x10] = 64, |
| 74 | [0x30] = 80, |
| 75 | [0x50] = 96, |
| 76 | [0x70] = 112, |
| 77 | [0x11] = 128, |
| 78 | }; |
| 79 | |
Angel Pons | 5d92aa5 | 2020-10-14 00:02:37 +0200 | [diff] [blame] | 80 | /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate |
| 81 | * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 82 | * when a core is woken up. */ |
| 83 | static int pcode_ready(void) |
| 84 | { |
| 85 | int wait_count; |
| 86 | const int delay_step = 10; |
| 87 | |
| 88 | wait_count = 0; |
| 89 | do { |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 90 | if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 91 | return 0; |
| 92 | wait_count += delay_step; |
| 93 | udelay(delay_step); |
| 94 | } while (wait_count < 1000); |
| 95 | |
| 96 | return -1; |
| 97 | } |
| 98 | |
| 99 | static void calibrate_24mhz_bclk(void) |
| 100 | { |
| 101 | int err_code; |
| 102 | |
| 103 | if (pcode_ready() < 0) { |
| 104 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 105 | return; |
| 106 | } |
| 107 | |
| 108 | /* A non-zero value initiates the PCODE calibration. */ |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 109 | mchbar_write32(BIOS_MAILBOX_DATA, ~0); |
| 110 | mchbar_write32(BIOS_MAILBOX_INTERFACE, |
| 111 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL); |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 112 | |
| 113 | if (pcode_ready() < 0) { |
| 114 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 115 | return; |
| 116 | } |
| 117 | |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 118 | err_code = mchbar_read32(BIOS_MAILBOX_INTERFACE) & 0xff; |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 119 | |
Angel Pons | 5d92aa5 | 2020-10-14 00:02:37 +0200 | [diff] [blame] | 120 | printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 121 | err_code); |
| 122 | |
| 123 | /* Read the calibrated value. */ |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 124 | mchbar_write32(BIOS_MAILBOX_INTERFACE, |
| 125 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION); |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 126 | |
| 127 | if (pcode_ready() < 0) { |
| 128 | printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); |
| 129 | return; |
| 130 | } |
| 131 | |
Angel Pons | 5d92aa5 | 2020-10-14 00:02:37 +0200 | [diff] [blame] | 132 | printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 133 | mchbar_read32(BIOS_MAILBOX_DATA)); |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 134 | } |
| 135 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 136 | static u32 pcode_mailbox_read(u32 command) |
| 137 | { |
| 138 | if (pcode_ready() < 0) { |
| 139 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 140 | return 0; |
| 141 | } |
| 142 | |
| 143 | /* Send command and start transaction */ |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 144 | mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY); |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 145 | |
| 146 | if (pcode_ready() < 0) { |
| 147 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | /* Read mailbox */ |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 152 | return mchbar_read32(BIOS_MAILBOX_DATA); |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 153 | } |
| 154 | |
Angel Pons | 1c7ba62 | 2020-10-29 00:01:29 +0100 | [diff] [blame] | 155 | static int pcode_mailbox_write(u32 command, u32 data) |
| 156 | { |
| 157 | if (pcode_ready() < 0) { |
| 158 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 159 | return -1; |
| 160 | } |
| 161 | |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 162 | mchbar_write32(BIOS_MAILBOX_DATA, data); |
Angel Pons | 1c7ba62 | 2020-10-29 00:01:29 +0100 | [diff] [blame] | 163 | |
| 164 | /* Send command and start transaction */ |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 165 | mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY); |
Angel Pons | 1c7ba62 | 2020-10-29 00:01:29 +0100 | [diff] [blame] | 166 | |
| 167 | if (pcode_ready() < 0) { |
| 168 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 169 | return -1; |
| 170 | } |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 175 | static struct device *cpu_cluster; |
| 176 | |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 177 | static void initialize_vr_config(void) |
| 178 | { |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 179 | struct cpu_vr_config vr_config = { 0 }; |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 180 | msr_t msr; |
| 181 | |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 182 | /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ |
| 183 | const struct cpu_intel_haswell_config *conf = cpu_cluster->chip_info; |
| 184 | vr_config = conf->vr_config; |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 185 | |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 186 | printk(BIOS_DEBUG, "Initializing VR config.\n"); |
| 187 | |
| 188 | /* Configure VR_CURRENT_CONFIG. */ |
| 189 | msr = rdmsr(MSR_VR_CURRENT_CONFIG); |
| 190 | /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid |
| 191 | * on ULT systems. */ |
| 192 | msr.hi &= 0xc0000000; |
| 193 | msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ |
| 194 | msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ |
Angel Pons | 9dcd1c1 | 2020-10-28 22:41:26 +0100 | [diff] [blame] | 195 | msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 196 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 197 | if (haswell_is_ult()) |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 198 | msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ |
| 199 | /* Leave the max instantaneous current limit (12:0) to default. */ |
| 200 | wrmsr(MSR_VR_CURRENT_CONFIG, msr); |
| 201 | |
| 202 | /* Configure VR_MISC_CONFIG MSR. */ |
| 203 | msr = rdmsr(MSR_VR_MISC_CONFIG); |
| 204 | /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ |
| 205 | msr.hi &= ~(0x3ff << (40 - 32)); |
| 206 | msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ |
| 207 | /* Set IOUT_OFFSET to 0. */ |
| 208 | msr.hi &= ~0xff; |
| 209 | /* Set exit ramp rate to fast. */ |
| 210 | msr.hi |= (1 << (50 - 32)); |
| 211 | /* Set entry ramp rate to slow. */ |
| 212 | msr.hi &= ~(1 << (51 - 32)); |
| 213 | /* Enable decay mode on C-state entry. */ |
| 214 | msr.hi |= (1 << (52 - 32)); |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 215 | /* Set the slow ramp rate */ |
Tristan Corrick | fdf907e | 2018-10-31 02:27:12 +1300 | [diff] [blame] | 216 | if (haswell_is_ult()) { |
Tristan Corrick | fdf907e | 2018-10-31 02:27:12 +1300 | [diff] [blame] | 217 | msr.hi &= ~(0x3 << (53 - 32)); |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 218 | /* Configure the C-state exit ramp rate. */ |
| 219 | if (vr_config.slow_ramp_rate_enable) { |
| 220 | /* Configured slow ramp rate. */ |
| 221 | msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); |
| 222 | /* Set exit ramp rate to slow. */ |
| 223 | msr.hi &= ~(1 << (50 - 32)); |
| 224 | } else { |
| 225 | /* Fast ramp rate / 4. */ |
| 226 | msr.hi |= (1 << (53 - 32)); |
| 227 | } |
Tristan Corrick | fdf907e | 2018-10-31 02:27:12 +1300 | [diff] [blame] | 228 | } |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 229 | /* Set MIN_VID (31:24) to allow CPU to have full control. */ |
| 230 | msr.lo &= ~0xff000000; |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 231 | msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 232 | wrmsr(MSR_VR_MISC_CONFIG, msr); |
| 233 | |
| 234 | /* Configure VR_MISC_CONFIG2 MSR. */ |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 235 | if (!haswell_is_ult()) |
| 236 | return; |
| 237 | |
| 238 | msr = rdmsr(MSR_VR_MISC_CONFIG2); |
| 239 | msr.lo &= ~0xffff; |
| 240 | /* Allow CPU to control minimum voltage completely (15:8) and |
Angel Pons | c86b119 | 2020-10-28 23:53:45 +0100 | [diff] [blame] | 241 | set the fast ramp voltage in 10mV steps. */ |
| 242 | if (cpu_family_model() == BROADWELL_FAMILY_ULT) |
| 243 | msr.lo |= 0x006a; /* 1.56V */ |
| 244 | else |
| 245 | msr.lo |= 0x006f; /* 1.60V */ |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 246 | wrmsr(MSR_VR_MISC_CONFIG2, msr); |
Angel Pons | 1c7ba62 | 2020-10-29 00:01:29 +0100 | [diff] [blame] | 247 | |
| 248 | /* Set C9/C10 VCC Min */ |
| 249 | pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 250 | } |
| 251 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 252 | static void configure_pch_power_sharing(void) |
| 253 | { |
| 254 | u32 pch_power, pch_power_ext, pmsync, pmsync2; |
| 255 | int i; |
| 256 | |
| 257 | /* Read PCH Power levels from PCODE */ |
| 258 | pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); |
| 259 | pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); |
| 260 | |
| 261 | printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 262 | pch_power, pch_power_ext); |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 263 | |
| 264 | pmsync = RCBA32(PMSYNC_CONFIG); |
| 265 | pmsync2 = RCBA32(PMSYNC_CONFIG2); |
| 266 | |
| 267 | /* Program PMSYNC_TPR_CONFIG PCH power limit values |
| 268 | * pmsync[0:4] = mailbox[0:5] |
| 269 | * pmsync[8:12] = mailbox[6:11] |
| 270 | * pmsync[16:20] = mailbox[12:17] |
| 271 | */ |
| 272 | for (i = 0; i < 3; i++) { |
| 273 | u32 level = pch_power & 0x3f; |
| 274 | pch_power >>= 6; |
| 275 | pmsync &= ~(0x1f << (i * 8)); |
| 276 | pmsync |= (level & 0x1f) << (i * 8); |
| 277 | } |
| 278 | RCBA32(PMSYNC_CONFIG) = pmsync; |
| 279 | |
| 280 | /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values |
| 281 | * pmsync2[0:4] = mailbox[23:18] |
| 282 | * pmsync2[8:12] = mailbox_ext[6:11] |
| 283 | * pmsync2[16:20] = mailbox_ext[12:17] |
| 284 | * pmsync2[24:28] = mailbox_ext[18:22] |
| 285 | */ |
| 286 | pmsync2 &= ~0x1f; |
| 287 | pmsync2 |= pch_power & 0x1f; |
| 288 | |
| 289 | for (i = 1; i < 4; i++) { |
| 290 | u32 level = pch_power_ext & 0x3f; |
| 291 | pch_power_ext >>= 6; |
| 292 | pmsync2 &= ~(0x1f << (i * 8)); |
| 293 | pmsync2 |= (level & 0x1f) << (i * 8); |
| 294 | } |
| 295 | RCBA32(PMSYNC_CONFIG2) = pmsync2; |
| 296 | } |
| 297 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 298 | int cpu_config_tdp_levels(void) |
| 299 | { |
| 300 | msr_t platform_info; |
| 301 | |
| 302 | /* Bits 34:33 indicate how many levels supported */ |
| 303 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 304 | return (platform_info.hi >> 1) & 3; |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * Configure processor power limits if possible |
| 309 | * This must be done AFTER set of BIOS_RESET_CPL |
| 310 | */ |
| 311 | void set_power_limits(u8 power_limit_1_time) |
| 312 | { |
| 313 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 314 | msr_t limit; |
Lee Leahy | 73a2894 | 2017-03-15 17:52:06 -0700 | [diff] [blame] | 315 | unsigned int power_unit; |
| 316 | unsigned int tdp, min_power, max_power, max_time; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 317 | u8 power_limit_1_val; |
| 318 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame] | 319 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 320 | power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 321 | |
| 322 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 323 | return; |
| 324 | |
| 325 | /* Get units */ |
| 326 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 327 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 328 | |
| 329 | /* Get power defaults for this SKU */ |
| 330 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 331 | tdp = msr.lo & 0x7fff; |
| 332 | min_power = (msr.lo >> 16) & 0x7fff; |
| 333 | max_power = msr.hi & 0x7fff; |
| 334 | max_time = (msr.hi >> 16) & 0x7f; |
| 335 | |
| 336 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 337 | |
| 338 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 339 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 340 | |
| 341 | if (min_power > 0 && tdp < min_power) |
| 342 | tdp = min_power; |
| 343 | |
| 344 | if (max_power > 0 && tdp > max_power) |
| 345 | tdp = max_power; |
| 346 | |
| 347 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 348 | |
| 349 | /* Set long term power limit to TDP */ |
| 350 | limit.lo = 0; |
| 351 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 352 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 353 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 354 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 355 | |
| 356 | /* Set short term power limit to 1.25 * TDP */ |
| 357 | limit.hi = 0; |
| 358 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 359 | limit.hi |= PKG_POWER_LIMIT_EN; |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 360 | /* Power limit 2 time is only programmable on server SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 361 | |
| 362 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 363 | |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 364 | /* Set power limit values in MCHBAR as well */ |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 365 | mchbar_write32(MCH_PKG_POWER_LIMIT_LO, limit.lo); |
| 366 | mchbar_write32(MCH_PKG_POWER_LIMIT_HI, limit.hi); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 367 | |
| 368 | /* Set DDR RAPL power limit by copying from MMIO to MSR */ |
Angel Pons | 7811a45 | 2021-03-27 20:05:22 +0100 | [diff] [blame] | 369 | msr.lo = mchbar_read32(MCH_DDR_POWER_LIMIT_LO); |
| 370 | msr.hi = mchbar_read32(MCH_DDR_POWER_LIMIT_HI); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 371 | wrmsr(MSR_DDR_RAPL_LIMIT, msr); |
| 372 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 373 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 374 | if (cpu_config_tdp_levels()) { |
| 375 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 376 | limit.hi = 0; |
| 377 | limit.lo = msr.lo & 0xff; |
| 378 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 379 | } |
| 380 | } |
| 381 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 382 | static void configure_c_states(void) |
| 383 | { |
Angel Pons | c89d2a28 | 2020-10-28 22:23:02 +0100 | [diff] [blame] | 384 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 385 | |
| 386 | const bool timed_mwait_capable = !!(msr.hi & TIMED_MWAIT_SUPPORTED); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 387 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 388 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 389 | msr.lo |= (1 << 30); // Package c-state Undemotion Enable |
| 390 | msr.lo |= (1 << 29); // Package c-state Demotion Enable |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 391 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 392 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 393 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 394 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
Angel Pons | cb70d83 | 2021-10-11 14:26:42 +0200 | [diff] [blame] | 395 | msr.lo |= (1 << 15); // Lock bits 15:0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 396 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
Angel Pons | c89d2a28 | 2020-10-28 22:23:02 +0100 | [diff] [blame] | 397 | |
| 398 | if (timed_mwait_capable) |
| 399 | msr.lo |= (1 << 31); // Timed MWAIT Enable |
| 400 | |
Duncan Laurie | 1c09710 | 2013-05-07 13:19:56 -0700 | [diff] [blame] | 401 | /* The deepest package c-state defaults to factory-configured value. */ |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 402 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 403 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 404 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 405 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 406 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 407 | |
| 408 | msr = rdmsr(MSR_POWER_CTL); |
| 409 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 410 | msr.lo |= (1 << 1); // C1E Enable |
| 411 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 412 | wrmsr(MSR_POWER_CTL, msr); |
| 413 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 414 | /* C-state Interrupt Response Latency Control 0 - package C3 latency */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 415 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 416 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; |
| 417 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 418 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 419 | /* C-state Interrupt Response Latency Control 1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 420 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 421 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
| 422 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 423 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 424 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 425 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 426 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
| 427 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 428 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 429 | /* Only Haswell ULT supports the 3-5 latency response registers */ |
| 430 | if (!haswell_is_ult()) |
| 431 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 432 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 433 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 434 | msr.hi = 0; |
| 435 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; |
| 436 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 437 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 438 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 439 | msr.hi = 0; |
| 440 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; |
| 441 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 442 | |
| 443 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 444 | msr.hi = 0; |
| 445 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; |
| 446 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 447 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 448 | |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 449 | static void configure_thermal_target(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 450 | { |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 451 | /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ |
| 452 | struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 453 | msr_t msr; |
| 454 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 455 | /* Set TCC activation offset if supported */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 456 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 457 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 458 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 459 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 460 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 461 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 462 | } |
| 463 | } |
| 464 | |
| 465 | static void configure_misc(void) |
| 466 | { |
| 467 | msr_t msr; |
| 468 | |
| 469 | msr = rdmsr(IA32_MISC_ENABLE); |
| 470 | msr.lo |= (1 << 0); /* Fast String enable */ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 471 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 472 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 473 | wrmsr(IA32_MISC_ENABLE, msr); |
| 474 | |
| 475 | /* Disable Thermal interrupts */ |
| 476 | msr.lo = 0; |
| 477 | msr.hi = 0; |
| 478 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 479 | |
| 480 | /* Enable package critical interrupt only */ |
| 481 | msr.lo = 1 << 4; |
| 482 | msr.hi = 0; |
| 483 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 484 | } |
| 485 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 486 | static void set_max_ratio(void) |
| 487 | { |
| 488 | msr_t msr, perf_ctl; |
| 489 | |
| 490 | perf_ctl.hi = 0; |
| 491 | |
| 492 | /* Check for configurable TDP option */ |
Angel Pons | 053deb8 | 2020-10-28 22:40:02 +0100 | [diff] [blame] | 493 | if (get_turbo_state() == TURBO_ENABLED) { |
| 494 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 495 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 496 | } else if (cpu_config_tdp_levels()) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 497 | /* Set to nominal TDP ratio */ |
| 498 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 499 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 500 | } else { |
| 501 | /* Platform Info bits 15:8 give max ratio */ |
| 502 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 503 | perf_ctl.lo = msr.lo & 0xff00; |
| 504 | } |
| 505 | wrmsr(IA32_PERF_CTL, perf_ctl); |
| 506 | |
Angel Pons | f6cf4927 | 2020-09-25 01:14:24 +0200 | [diff] [blame] | 507 | printk(BIOS_DEBUG, "CPU: frequency set to %d\n", |
Angel Pons | ca96549 | 2020-10-28 19:15:36 +0100 | [diff] [blame] | 508 | ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 509 | } |
| 510 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 511 | static void configure_mca(void) |
| 512 | { |
| 513 | msr_t msr; |
| 514 | int i; |
Felix Held | bad21a4 | 2021-07-13 01:55:52 +0200 | [diff] [blame] | 515 | const unsigned int num_banks = mca_get_bank_count(); |
Angel Pons | 1515a48 | 2021-06-13 22:33:06 +0200 | [diff] [blame] | 516 | |
| 517 | /* Enable all error reporting */ |
| 518 | msr.lo = msr.hi = ~0; |
| 519 | for (i = 0; i < num_banks; i++) |
Felix Held | 1b46e76 | 2021-07-13 00:54:32 +0200 | [diff] [blame] | 520 | wrmsr(IA32_MC_CTL(i), msr); |
Angel Pons | 1515a48 | 2021-06-13 22:33:06 +0200 | [diff] [blame] | 521 | |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 522 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 523 | * of these banks are core vs package scope. For now every CPU clears |
| 524 | * every bank. */ |
Felix Held | acbf154 | 2021-07-13 16:44:18 +0200 | [diff] [blame] | 525 | mca_clear_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 526 | } |
| 527 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 528 | /* All CPUs including BSP will run the following function. */ |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 529 | static void cpu_core_init(struct device *cpu) |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 530 | { |
| 531 | /* Clear out pending MCEs */ |
| 532 | configure_mca(); |
| 533 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 534 | enable_lapic_tpr(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 535 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 536 | /* Set virtualization based on Kconfig option */ |
Matt DeVillier | f9aed65 | 2018-12-15 15:57:33 -0600 | [diff] [blame] | 537 | set_vmx_and_lock(); |
Matt DeVillier | b2a14fb | 2014-07-07 18:48:16 -0500 | [diff] [blame] | 538 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 539 | /* Configure C States */ |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 540 | configure_c_states(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 541 | |
| 542 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 543 | configure_misc(); |
| 544 | |
| 545 | /* Thermal throttle activation offset */ |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 546 | configure_thermal_target(cpu); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 547 | |
| 548 | /* Enable Direct Cache Access */ |
| 549 | configure_dca_cap(); |
| 550 | |
| 551 | /* Set energy policy */ |
| 552 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 553 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 554 | /* Enable Turbo */ |
| 555 | enable_turbo(); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 556 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 557 | |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 558 | /* MP initialization support. */ |
| 559 | static const void *microcode_patch; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 560 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 561 | static void pre_mp_init(void) |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 562 | { |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 563 | /* Setup MTRRs based on physical address size. */ |
| 564 | x86_setup_mtrrs_with_detect(); |
| 565 | x86_mtrr_check(); |
| 566 | |
| 567 | initialize_vr_config(); |
| 568 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 569 | if (!haswell_is_ult()) |
| 570 | return; |
| 571 | |
| 572 | calibrate_24mhz_bclk(); |
| 573 | configure_pch_power_sharing(); |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 574 | } |
| 575 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 576 | static int get_cpu_count(void) |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 577 | { |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 578 | msr_t msr; |
Angel Pons | 04c497a | 2021-11-03 16:30:10 +0100 | [diff] [blame] | 579 | unsigned int num_threads; |
| 580 | unsigned int num_cores; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 581 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 582 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 583 | num_threads = (msr.lo >> 0) & 0xffff; |
| 584 | num_cores = (msr.lo >> 16) & 0xffff; |
| 585 | printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| 586 | num_cores, num_threads); |
| 587 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 588 | return num_threads; |
| 589 | } |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 590 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 591 | static void get_microcode_info(const void **microcode, int *parallel) |
| 592 | { |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 593 | microcode_patch = intel_microcode_find(); |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 594 | *microcode = microcode_patch; |
| 595 | *parallel = 1; |
| 596 | } |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 597 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 598 | static void per_cpu_smm_trigger(void) |
| 599 | { |
| 600 | /* Relocate the SMM handler. */ |
| 601 | smm_relocate(); |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 602 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 603 | /* After SMM relocation a 2nd microcode load is required. */ |
| 604 | intel_microcode_load_unlocked(microcode_patch); |
| 605 | } |
| 606 | |
| 607 | static void post_mp_init(void) |
| 608 | { |
Angel Pons | 053deb8 | 2020-10-28 22:40:02 +0100 | [diff] [blame] | 609 | /* Set Max Ratio */ |
| 610 | set_max_ratio(); |
| 611 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 612 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 613 | * start flowing. */ |
Kyösti Mälkki | 0778c86 | 2020-06-10 12:44:03 +0300 | [diff] [blame] | 614 | global_smi_enable(); |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 615 | |
| 616 | /* Lock down the SMRAM space. */ |
| 617 | smm_lock(); |
| 618 | } |
| 619 | |
| 620 | static const struct mp_ops mp_ops = { |
| 621 | .pre_mp_init = pre_mp_init, |
| 622 | .get_cpu_count = get_cpu_count, |
| 623 | .get_smm_info = smm_info, |
| 624 | .get_microcode_info = get_microcode_info, |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 625 | .pre_mp_smm_init = smm_initialize, |
| 626 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 627 | .relocation_handler = smm_relocation_handler, |
| 628 | .post_mp_init = post_mp_init, |
| 629 | }; |
| 630 | |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 631 | void mp_init_cpus(struct bus *cpu_bus) |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 632 | { |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 633 | cpu_cluster = cpu_bus->dev; |
Felix Held | 4dd7d11 | 2021-10-20 23:31:43 +0200 | [diff] [blame] | 634 | /* TODO: Handle mp_init_with_smm failure? */ |
| 635 | mp_init_with_smm(cpu_bus, &mp_ops); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 636 | } |
| 637 | |
| 638 | static struct device_operations cpu_dev_ops = { |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 639 | .init = cpu_core_init, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 640 | }; |
| 641 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 642 | static const struct cpu_device_id cpu_table[] = { |
Felix Held | 6a6ac1e | 2023-02-06 15:19:11 +0100 | [diff] [blame] | 643 | { X86_VENDOR_INTEL, CPUID_HASWELL_A0, CPUID_EXACT_MATCH_MASK }, |
| 644 | { X86_VENDOR_INTEL, CPUID_HASWELL_B0, CPUID_EXACT_MATCH_MASK }, |
| 645 | { X86_VENDOR_INTEL, CPUID_HASWELL_C0, CPUID_EXACT_MATCH_MASK }, |
| 646 | { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0, CPUID_EXACT_MATCH_MASK }, |
| 647 | { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0, CPUID_EXACT_MATCH_MASK }, |
| 648 | { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0, CPUID_EXACT_MATCH_MASK }, |
| 649 | { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0, CPUID_EXACT_MATCH_MASK }, |
| 650 | { X86_VENDOR_INTEL, CPUID_BROADWELL_C0, CPUID_EXACT_MATCH_MASK }, |
| 651 | { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_C0, CPUID_EXACT_MATCH_MASK }, |
| 652 | { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_D0, CPUID_EXACT_MATCH_MASK }, |
| 653 | { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_E0, CPUID_EXACT_MATCH_MASK }, |
Felix Held | 1e78165 | 2023-02-08 11:39:16 +0100 | [diff] [blame^] | 654 | CPU_TABLE_END |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 655 | }; |
| 656 | |
| 657 | static const struct cpu_driver driver __cpu_driver = { |
| 658 | .ops = &cpu_dev_ops, |
| 659 | .id_table = cpu_table, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 660 | }; |