Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 2 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 3 | #include <cpu/intel/post_codes.h> |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 4 | #include <cpu/x86/mtrr.h> |
| 5 | #include <cpu/x86/cache.h> |
| 6 | #include <cpu/x86/post_code.h> |
| 7 | |
Kyösti Mälkki | 7522a8f | 2020-11-20 16:47:38 +0200 | [diff] [blame] | 8 | .section .init |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 9 | .global bootblock_pre_c_entry |
| 10 | |
Patrick Rudolph | c439e07 | 2020-09-28 22:31:06 +0200 | [diff] [blame] | 11 | #include <cpu/intel/car/cache_as_ram_symbols.inc> |
| 12 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 13 | .code32 |
| 14 | _cache_as_ram_setup: |
| 15 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 16 | bootblock_pre_c_entry: |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 17 | |
| 18 | cache_as_ram: |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 19 | post_code(POSTCODE_BOOTBLOCK_CAR) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 20 | |
| 21 | /* Send INIT IPI to all excluding ourself. */ |
| 22 | movl $0x000C4500, %eax |
| 23 | movl $0xFEE00300, %esi |
| 24 | movl %eax, (%esi) |
| 25 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 26 | /* All CPUs need to be in Wait for SIPI state */ |
| 27 | wait_for_sipi: |
| 28 | movl (%esi), %eax |
| 29 | bt $12, %eax |
| 30 | jc wait_for_sipi |
| 31 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 32 | post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS) |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 33 | |
| 34 | /* Clear/disable fixed MTRRs */ |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 35 | mov $fixed_mtrr_list, %ebx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 36 | xor %eax, %eax |
| 37 | xor %edx, %edx |
| 38 | |
| 39 | clear_fixed_mtrr: |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 40 | movzwl (%ebx), %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 41 | wrmsr |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 42 | add $2, %ebx |
| 43 | cmp $fixed_mtrr_list_end, %ebx |
| 44 | jl clear_fixed_mtrr |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 45 | |
Elyes HAOUAS | 02820ca | 2018-09-30 07:44:39 +0200 | [diff] [blame] | 46 | /* Figure out how many MTRRs we have, and clear them out */ |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 47 | mov $MTRR_CAP_MSR, %ecx |
| 48 | rdmsr |
| 49 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 50 | mov $MTRR_PHYS_BASE(0), %ecx |
| 51 | xor %eax, %eax |
| 52 | xor %edx, %edx |
| 53 | |
| 54 | clear_var_mtrr: |
| 55 | wrmsr |
| 56 | inc %ecx |
| 57 | wrmsr |
| 58 | inc %ecx |
| 59 | dec %ebx |
| 60 | jnz clear_var_mtrr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 61 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 62 | post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 63 | /* Configure the default memory type to uncacheable. */ |
| 64 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 65 | rdmsr |
| 66 | andl $(~0x00000cff), %eax |
| 67 | wrmsr |
| 68 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 69 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
| 70 | movl $0x80000008, %eax |
| 71 | cpuid |
| 72 | movb %al, %cl |
| 73 | sub $32, %cl |
| 74 | movl $1, %edx |
| 75 | shl %cl, %edx |
| 76 | subl $1, %edx |
| 77 | |
| 78 | /* Preload high word of address mask (in %edx) for Variable |
| 79 | MTRRs 0 and 1. */ |
| 80 | addrsize_set_high: |
| 81 | xorl %eax, %eax |
| 82 | movl $MTRR_PHYS_MASK(0), %ecx |
| 83 | wrmsr |
| 84 | movl $MTRR_PHYS_MASK(1), %ecx |
| 85 | wrmsr |
| 86 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 87 | post_code(POSTCODE_SOC_SET_MTRR_BASE) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 88 | /* Set Cache-as-RAM base address. */ |
| 89 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 90 | movl $_car_mtrr_start, %eax |
| 91 | orl $MTRR_TYPE_WRBACK, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 92 | xorl %edx, %edx |
| 93 | wrmsr |
| 94 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 95 | post_code(POSTCODE_SOC_SET_MTRR_MASK) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 96 | /* Set Cache-as-RAM mask. */ |
| 97 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 98 | rdmsr |
Patrick Rudolph | c439e07 | 2020-09-28 22:31:06 +0200 | [diff] [blame] | 99 | movl car_mtrr_mask, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 100 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 101 | wrmsr |
| 102 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 103 | post_code(POSTCODE_SOC_ENABLE_MTRRS) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 104 | |
| 105 | /* Enable MTRR. */ |
| 106 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 107 | rdmsr |
| 108 | orl $MTRR_DEF_TYPE_EN, %eax |
| 109 | wrmsr |
| 110 | |
| 111 | /* Enable L2 cache. */ |
| 112 | movl $0x11e, %ecx |
| 113 | rdmsr |
| 114 | orl $(1 << 8), %eax |
| 115 | wrmsr |
| 116 | |
| 117 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 118 | movl %cr0, %eax |
| 119 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 120 | invd |
| 121 | movl %eax, %cr0 |
| 122 | |
| 123 | /* Clear the cache memory region. This will also fill up the cache. */ |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 124 | cld |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 125 | xorl %eax, %eax |
Patrick Rudolph | c439e07 | 2020-09-28 22:31:06 +0200 | [diff] [blame] | 126 | movl car_mtrr_start, %edi |
| 127 | movl car_mtrr_size, %ecx |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 128 | shr $2, %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 129 | rep stosl |
| 130 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 131 | post_code(POSTCODE_SOC_DISABLE_CACHE) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 132 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 133 | movl %cr0, %eax |
| 134 | orl $CR0_CacheDisable, %eax |
| 135 | movl %eax, %cr0 |
| 136 | |
| 137 | /* Enable cache for our code in Flash because we do XIP here */ |
| 138 | movl $MTRR_PHYS_BASE(1), %ecx |
| 139 | xorl %edx, %edx |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 140 | movl $_program, %eax |
Patrick Rudolph | c439e07 | 2020-09-28 22:31:06 +0200 | [diff] [blame] | 141 | andl xip_mtrr_mask, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 142 | orl $MTRR_TYPE_WRPROT, %eax |
| 143 | wrmsr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 144 | movl $MTRR_PHYS_MASK(1), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 145 | rdmsr |
Patrick Rudolph | c439e07 | 2020-09-28 22:31:06 +0200 | [diff] [blame] | 146 | movl xip_mtrr_mask, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 147 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 148 | wrmsr |
| 149 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 150 | post_code(POSTCODE_SOC_ENABLE_CACHE) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 151 | /* Enable cache. */ |
| 152 | movl %cr0, %eax |
| 153 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 154 | movl %eax, %cr0 |
| 155 | |
| 156 | /* Setup the stack. */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 157 | mov $_ecar_stack, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 158 | |
| 159 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 160 | the pushes below. */ |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 161 | andl $0xfffffff0, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 162 | subl $4, %esp |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 163 | |
Patrick Rudolph | c439e07 | 2020-09-28 22:31:06 +0200 | [diff] [blame] | 164 | #if ENV_X86_64 |
| 165 | |
| 166 | #include <cpu/x86/64bit/entry64.inc> |
| 167 | |
| 168 | movd %mm2, %rdi |
| 169 | shlq $32, %rdi |
| 170 | movd %mm1, %rsi |
| 171 | or %rsi, %rdi |
| 172 | movd %mm0, %rsi |
| 173 | #else |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 174 | /* push TSC and BIST to stack */ |
| 175 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 176 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 177 | movd %mm2, %eax |
| 178 | pushl %eax /* tsc[63:32] */ |
| 179 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 180 | pushl %eax /* tsc[31:0] */ |
Patrick Rudolph | c439e07 | 2020-09-28 22:31:06 +0200 | [diff] [blame] | 181 | #endif |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 182 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 183 | before_c_entry: |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 184 | post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 185 | call bootblock_c_entry_bist |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 186 | |
| 187 | /* Should never see this postcode */ |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 188 | post_code(POSTCODE_DEAD_CODE) |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 189 | |
| 190 | .Lhlt: |
| 191 | hlt |
| 192 | jmp .Lhlt |
| 193 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 194 | fixed_mtrr_list: |
| 195 | .word MTRR_FIX_64K_00000 |
| 196 | .word MTRR_FIX_16K_80000 |
| 197 | .word MTRR_FIX_16K_A0000 |
| 198 | .word MTRR_FIX_4K_C0000 |
| 199 | .word MTRR_FIX_4K_C8000 |
| 200 | .word MTRR_FIX_4K_D0000 |
| 201 | .word MTRR_FIX_4K_D8000 |
| 202 | .word MTRR_FIX_4K_E0000 |
| 203 | .word MTRR_FIX_4K_E8000 |
| 204 | .word MTRR_FIX_4K_F0000 |
| 205 | .word MTRR_FIX_4K_F8000 |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 206 | fixed_mtrr_list_end: |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 207 | |
| 208 | _cache_as_ram_setup_end: |