| Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <cpu/x86/mtrr.h> |
| 18 | #include <cpu/x86/cache.h> |
| 19 | #include <cpu/x86/post_code.h> |
| 20 | |
| 21 | #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) |
| 22 | |
| 23 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 24 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 25 | |
| 26 | .code32 |
| 27 | _cache_as_ram_setup: |
| 28 | |
| 29 | /* Save the BIST result. */ |
| 30 | movl %eax, %ebp |
| 31 | |
| 32 | cache_as_ram: |
| 33 | post_code(0x20) |
| 34 | |
| 35 | /* Send INIT IPI to all excluding ourself. */ |
| 36 | movl $0x000C4500, %eax |
| 37 | movl $0xFEE00300, %esi |
| 38 | movl %eax, (%esi) |
| 39 | |
| 40 | /* Zero out all fixed range and variable range MTRRs. */ |
| 41 | movl $mtrr_table, %esi |
| 42 | movl $((mtrr_table_end - mtrr_table) >> 1), %edi |
| 43 | xorl %eax, %eax |
| 44 | xorl %edx, %edx |
| 45 | clear_mtrrs: |
| 46 | movw (%esi), %bx |
| 47 | movzx %bx, %ecx |
| 48 | wrmsr |
| 49 | add $2, %esi |
| 50 | dec %edi |
| 51 | jnz clear_mtrrs |
| 52 | |
| 53 | post_code(0x22) |
| 54 | /* Configure the default memory type to uncacheable. */ |
| 55 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 56 | rdmsr |
| 57 | andl $(~0x00000cff), %eax |
| 58 | wrmsr |
| 59 | |
| 60 | post_code(0x23) |
| 61 | /* Set Cache-as-RAM base address. */ |
| 62 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 63 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 64 | xorl %edx, %edx |
| 65 | wrmsr |
| 66 | |
| 67 | post_code(0x24) |
| 68 | /* Set Cache-as-RAM mask. */ |
| 69 | movl $(MTRR_PHYS_MASK(0)), %ecx |
| 70 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 71 | movl $CPU_PHYSMASK_HI, %edx |
| 72 | wrmsr |
| 73 | |
| 74 | post_code(0x25) |
| 75 | |
| 76 | /* Enable MTRR. */ |
| 77 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 78 | rdmsr |
| 79 | orl $MTRR_DEF_TYPE_EN, %eax |
| 80 | wrmsr |
| 81 | |
| 82 | /* Enable L2 cache. */ |
| 83 | movl $0x11e, %ecx |
| 84 | rdmsr |
| 85 | orl $(1 << 8), %eax |
| 86 | wrmsr |
| 87 | |
| 88 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 89 | movl %cr0, %eax |
| 90 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 91 | invd |
| 92 | movl %eax, %cr0 |
| 93 | |
| 94 | /* Clear the cache memory region. This will also fill up the cache. */ |
| 95 | movl $CACHE_AS_RAM_BASE, %esi |
| 96 | movl %esi, %edi |
| 97 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
| 98 | // movl $0x23322332, %eax |
| 99 | xorl %eax, %eax |
| 100 | rep stosl |
| 101 | |
| 102 | post_code(0x26) |
| 103 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 104 | movl %cr0, %eax |
| 105 | orl $CR0_CacheDisable, %eax |
| 106 | movl %eax, %cr0 |
| 107 | |
| 108 | /* Enable cache for our code in Flash because we do XIP here */ |
| 109 | movl $MTRR_PHYS_BASE(1), %ecx |
| 110 | xorl %edx, %edx |
| 111 | /* |
| 112 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 113 | * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 114 | */ |
| 115 | movl $copy_and_run, %eax |
| 116 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 117 | orl $MTRR_TYPE_WRPROT, %eax |
| 118 | wrmsr |
| 119 | |
| 120 | movl $MTRR_PHYS_MASK(1), %ecx |
| 121 | movl $CPU_PHYSMASK_HI, %edx |
| 122 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 123 | wrmsr |
| 124 | |
| 125 | post_code(0x28) |
| 126 | /* Enable cache. */ |
| 127 | movl %cr0, %eax |
| 128 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 129 | movl %eax, %cr0 |
| 130 | |
| 131 | /* Setup the stack. */ |
| 132 | movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax |
| 133 | movl %eax, %esp |
| 134 | |
| 135 | /* Restore the BIST result. */ |
| 136 | movl %ebp, %eax |
| 137 | movl %esp, %ebp |
| 138 | pushl %eax |
| 139 | |
| 140 | before_romstage: |
| 141 | post_code(0x29) |
| 142 | /* Call romstage.c main function. */ |
| 143 | call romstage_main |
| 144 | |
| 145 | /* Should never see this postcode */ |
| 146 | post_code(POST_DEAD_CODE) |
| 147 | |
| 148 | .Lhlt: |
| 149 | hlt |
| 150 | jmp .Lhlt |
| 151 | |
| 152 | mtrr_table: |
| 153 | /* Fixed MTRRs */ |
| 154 | .word 0x250, 0x258, 0x259 |
| 155 | .word 0x268, 0x269, 0x26A |
| 156 | .word 0x26B, 0x26C, 0x26D |
| 157 | .word 0x26E, 0x26F |
| 158 | /* Variable MTRRs */ |
| 159 | .word 0x200, 0x201, 0x202, 0x203 |
| 160 | .word 0x204, 0x205, 0x206, 0x207 |
| 161 | .word 0x208, 0x209, 0x20A, 0x20B |
| 162 | .word 0x20C, 0x20D, 0x20E, 0x20F |
| 163 | mtrr_table_end: |
| 164 | |
| 165 | _cache_as_ram_setup_end: |