Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 6 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <cpu/x86/mtrr.h> |
| 19 | #include <cpu/x86/cache.h> |
| 20 | #include <cpu/x86/post_code.h> |
| 21 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 22 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 23 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 24 | |
| 25 | .code32 |
| 26 | _cache_as_ram_setup: |
| 27 | |
| 28 | /* Save the BIST result. */ |
| 29 | movl %eax, %ebp |
| 30 | |
| 31 | cache_as_ram: |
| 32 | post_code(0x20) |
| 33 | |
| 34 | /* Send INIT IPI to all excluding ourself. */ |
| 35 | movl $0x000C4500, %eax |
| 36 | movl $0xFEE00300, %esi |
| 37 | movl %eax, (%esi) |
| 38 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 39 | /* All CPUs need to be in Wait for SIPI state */ |
| 40 | wait_for_sipi: |
| 41 | movl (%esi), %eax |
| 42 | bt $12, %eax |
| 43 | jc wait_for_sipi |
| 44 | |
| 45 | post_code(0x22) |
| 46 | |
| 47 | /* Clear/disable fixed MTRRs */ |
| 48 | mov $fixed_mtrr_list_size, %ebx |
| 49 | xor %eax, %eax |
| 50 | xor %edx, %edx |
| 51 | |
| 52 | clear_fixed_mtrr: |
| 53 | add $-2, %ebx |
| 54 | movzwl fixed_mtrr_list(%ebx), %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 55 | wrmsr |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 56 | jnz clear_fixed_mtrr |
| 57 | |
| 58 | /* Figure put how many MTRRs we have, and clear them out */ |
| 59 | mov $MTRR_CAP_MSR, %ecx |
| 60 | rdmsr |
| 61 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 62 | mov $MTRR_PHYS_BASE(0), %ecx |
| 63 | xor %eax, %eax |
| 64 | xor %edx, %edx |
| 65 | |
| 66 | clear_var_mtrr: |
| 67 | wrmsr |
| 68 | inc %ecx |
| 69 | wrmsr |
| 70 | inc %ecx |
| 71 | dec %ebx |
| 72 | jnz clear_var_mtrr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 73 | |
| 74 | post_code(0x22) |
| 75 | /* Configure the default memory type to uncacheable. */ |
| 76 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 77 | rdmsr |
| 78 | andl $(~0x00000cff), %eax |
| 79 | wrmsr |
| 80 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 81 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
| 82 | movl $0x80000008, %eax |
| 83 | cpuid |
| 84 | movb %al, %cl |
| 85 | sub $32, %cl |
| 86 | movl $1, %edx |
| 87 | shl %cl, %edx |
| 88 | subl $1, %edx |
| 89 | |
| 90 | /* Preload high word of address mask (in %edx) for Variable |
| 91 | MTRRs 0 and 1. */ |
| 92 | addrsize_set_high: |
| 93 | xorl %eax, %eax |
| 94 | movl $MTRR_PHYS_MASK(0), %ecx |
| 95 | wrmsr |
| 96 | movl $MTRR_PHYS_MASK(1), %ecx |
| 97 | wrmsr |
| 98 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 99 | post_code(0x23) |
| 100 | /* Set Cache-as-RAM base address. */ |
| 101 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 102 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 103 | xorl %edx, %edx |
| 104 | wrmsr |
| 105 | |
| 106 | post_code(0x24) |
| 107 | /* Set Cache-as-RAM mask. */ |
| 108 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 109 | rdmsr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 110 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 111 | wrmsr |
| 112 | |
| 113 | post_code(0x25) |
| 114 | |
| 115 | /* Enable MTRR. */ |
| 116 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 117 | rdmsr |
| 118 | orl $MTRR_DEF_TYPE_EN, %eax |
| 119 | wrmsr |
| 120 | |
| 121 | /* Enable L2 cache. */ |
| 122 | movl $0x11e, %ecx |
| 123 | rdmsr |
| 124 | orl $(1 << 8), %eax |
| 125 | wrmsr |
| 126 | |
| 127 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 128 | movl %cr0, %eax |
| 129 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 130 | invd |
| 131 | movl %eax, %cr0 |
| 132 | |
| 133 | /* Clear the cache memory region. This will also fill up the cache. */ |
| 134 | movl $CACHE_AS_RAM_BASE, %esi |
| 135 | movl %esi, %edi |
| 136 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 137 | xorl %eax, %eax |
| 138 | rep stosl |
| 139 | |
| 140 | post_code(0x26) |
| 141 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 142 | movl %cr0, %eax |
| 143 | orl $CR0_CacheDisable, %eax |
| 144 | movl %eax, %cr0 |
| 145 | |
| 146 | /* Enable cache for our code in Flash because we do XIP here */ |
| 147 | movl $MTRR_PHYS_BASE(1), %ecx |
| 148 | xorl %edx, %edx |
| 149 | /* |
| 150 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 151 | * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 152 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame^] | 153 | movl $_program, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 154 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 155 | orl $MTRR_TYPE_WRPROT, %eax |
| 156 | wrmsr |
| 157 | |
| 158 | movl $MTRR_PHYS_MASK(1), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 159 | rdmsr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 160 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 161 | wrmsr |
| 162 | |
| 163 | post_code(0x28) |
| 164 | /* Enable cache. */ |
| 165 | movl %cr0, %eax |
| 166 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 167 | movl %eax, %cr0 |
| 168 | |
| 169 | /* Setup the stack. */ |
| 170 | movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax |
| 171 | movl %eax, %esp |
| 172 | |
| 173 | /* Restore the BIST result. */ |
| 174 | movl %ebp, %eax |
| 175 | movl %esp, %ebp |
| 176 | pushl %eax |
| 177 | |
| 178 | before_romstage: |
| 179 | post_code(0x29) |
| 180 | /* Call romstage.c main function. */ |
| 181 | call romstage_main |
| 182 | |
| 183 | /* Should never see this postcode */ |
| 184 | post_code(POST_DEAD_CODE) |
| 185 | |
| 186 | .Lhlt: |
| 187 | hlt |
| 188 | jmp .Lhlt |
| 189 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 190 | fixed_mtrr_list: |
| 191 | .word MTRR_FIX_64K_00000 |
| 192 | .word MTRR_FIX_16K_80000 |
| 193 | .word MTRR_FIX_16K_A0000 |
| 194 | .word MTRR_FIX_4K_C0000 |
| 195 | .word MTRR_FIX_4K_C8000 |
| 196 | .word MTRR_FIX_4K_D0000 |
| 197 | .word MTRR_FIX_4K_D8000 |
| 198 | .word MTRR_FIX_4K_E0000 |
| 199 | .word MTRR_FIX_4K_E8000 |
| 200 | .word MTRR_FIX_4K_F0000 |
| 201 | .word MTRR_FIX_4K_F8000 |
| 202 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 203 | |
| 204 | _cache_as_ram_setup_end: |