src/*/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 316b703..9c60308 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -29,7 +29,7 @@
bt $12, %eax
jc wait_for_sipi
- post_code(POST_SOC_CLEAR_FIXED_MTRRS)
+ post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
/* Clear/disable fixed MTRRs */
mov $fixed_mtrr_list, %ebx
@@ -59,7 +59,7 @@
dec %ebx
jnz clear_var_mtrr
- post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+ post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
@@ -84,7 +84,7 @@
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
- post_code(POST_SOC_SET_MTRR_BASE)
+ post_code(POSTCODE_SOC_SET_MTRR_BASE)
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
movl $_car_mtrr_start, %eax
@@ -92,7 +92,7 @@
xorl %edx, %edx
wrmsr
- post_code(POST_SOC_SET_MTRR_MASK)
+ post_code(POSTCODE_SOC_SET_MTRR_MASK)
/* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
@@ -100,7 +100,7 @@
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_MTRRS)
+ post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -128,7 +128,7 @@
shr $2, %ecx
rep stosl
- post_code(POST_SOC_DISABLE_CACHE)
+ post_code(POSTCODE_SOC_DISABLE_CACHE)
/* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -147,7 +147,7 @@
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_CACHE)
+ post_code(POSTCODE_SOC_ENABLE_CACHE)
/* Enable cache. */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -181,7 +181,7 @@
#endif
before_c_entry:
- post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
call bootblock_c_entry_bist
/* Should never see this postcode */