Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 2 | |
| 3 | #include <cpu/x86/mtrr.h> |
| 4 | #include <cpu/x86/cache.h> |
| 5 | #include <cpu/x86/post_code.h> |
| 6 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 7 | .global bootblock_pre_c_entry |
| 8 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 9 | .code32 |
| 10 | _cache_as_ram_setup: |
| 11 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 12 | bootblock_pre_c_entry: |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 13 | |
| 14 | cache_as_ram: |
| 15 | post_code(0x20) |
| 16 | |
| 17 | /* Send INIT IPI to all excluding ourself. */ |
| 18 | movl $0x000C4500, %eax |
| 19 | movl $0xFEE00300, %esi |
| 20 | movl %eax, (%esi) |
| 21 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 22 | /* All CPUs need to be in Wait for SIPI state */ |
| 23 | wait_for_sipi: |
| 24 | movl (%esi), %eax |
| 25 | bt $12, %eax |
| 26 | jc wait_for_sipi |
| 27 | |
| 28 | post_code(0x22) |
| 29 | |
| 30 | /* Clear/disable fixed MTRRs */ |
| 31 | mov $fixed_mtrr_list_size, %ebx |
| 32 | xor %eax, %eax |
| 33 | xor %edx, %edx |
| 34 | |
| 35 | clear_fixed_mtrr: |
| 36 | add $-2, %ebx |
| 37 | movzwl fixed_mtrr_list(%ebx), %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 38 | wrmsr |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 39 | jnz clear_fixed_mtrr |
| 40 | |
Elyes HAOUAS | 02820ca | 2018-09-30 07:44:39 +0200 | [diff] [blame] | 41 | /* Figure out how many MTRRs we have, and clear them out */ |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 42 | mov $MTRR_CAP_MSR, %ecx |
| 43 | rdmsr |
| 44 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 45 | mov $MTRR_PHYS_BASE(0), %ecx |
| 46 | xor %eax, %eax |
| 47 | xor %edx, %edx |
| 48 | |
| 49 | clear_var_mtrr: |
| 50 | wrmsr |
| 51 | inc %ecx |
| 52 | wrmsr |
| 53 | inc %ecx |
| 54 | dec %ebx |
| 55 | jnz clear_var_mtrr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 56 | |
| 57 | post_code(0x22) |
| 58 | /* Configure the default memory type to uncacheable. */ |
| 59 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 60 | rdmsr |
| 61 | andl $(~0x00000cff), %eax |
| 62 | wrmsr |
| 63 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 64 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
| 65 | movl $0x80000008, %eax |
| 66 | cpuid |
| 67 | movb %al, %cl |
| 68 | sub $32, %cl |
| 69 | movl $1, %edx |
| 70 | shl %cl, %edx |
| 71 | subl $1, %edx |
| 72 | |
| 73 | /* Preload high word of address mask (in %edx) for Variable |
| 74 | MTRRs 0 and 1. */ |
| 75 | addrsize_set_high: |
| 76 | xorl %eax, %eax |
| 77 | movl $MTRR_PHYS_MASK(0), %ecx |
| 78 | wrmsr |
| 79 | movl $MTRR_PHYS_MASK(1), %ecx |
| 80 | wrmsr |
| 81 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 82 | post_code(0x23) |
| 83 | /* Set Cache-as-RAM base address. */ |
| 84 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 85 | movl $_car_mtrr_start, %eax |
| 86 | orl $MTRR_TYPE_WRBACK, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 87 | xorl %edx, %edx |
| 88 | wrmsr |
| 89 | |
| 90 | post_code(0x24) |
| 91 | /* Set Cache-as-RAM mask. */ |
| 92 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 93 | rdmsr |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 94 | movl $_car_mtrr_mask, %eax |
| 95 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 96 | wrmsr |
| 97 | |
| 98 | post_code(0x25) |
| 99 | |
| 100 | /* Enable MTRR. */ |
| 101 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 102 | rdmsr |
| 103 | orl $MTRR_DEF_TYPE_EN, %eax |
| 104 | wrmsr |
| 105 | |
| 106 | /* Enable L2 cache. */ |
| 107 | movl $0x11e, %ecx |
| 108 | rdmsr |
| 109 | orl $(1 << 8), %eax |
| 110 | wrmsr |
| 111 | |
| 112 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 113 | movl %cr0, %eax |
| 114 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 115 | invd |
| 116 | movl %eax, %cr0 |
| 117 | |
| 118 | /* Clear the cache memory region. This will also fill up the cache. */ |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 119 | cld |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 120 | xorl %eax, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 121 | movl $_car_mtrr_start, %edi |
| 122 | movl $_car_mtrr_size, %ecx |
| 123 | shr $2, %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 124 | rep stosl |
| 125 | |
| 126 | post_code(0x26) |
| 127 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 128 | movl %cr0, %eax |
| 129 | orl $CR0_CacheDisable, %eax |
| 130 | movl %eax, %cr0 |
| 131 | |
| 132 | /* Enable cache for our code in Flash because we do XIP here */ |
| 133 | movl $MTRR_PHYS_BASE(1), %ecx |
| 134 | xorl %edx, %edx |
| 135 | /* |
| 136 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
Stefan Tauner | de02878 | 2018-08-19 20:02:05 +0200 | [diff] [blame] | 137 | * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 138 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 139 | movl $_program, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 140 | andl $_xip_mtrr_mask, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 141 | orl $MTRR_TYPE_WRPROT, %eax |
| 142 | wrmsr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 143 | movl $MTRR_PHYS_MASK(1), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 144 | rdmsr |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 145 | movl $_xip_mtrr_mask, %eax |
| 146 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 147 | wrmsr |
| 148 | |
| 149 | post_code(0x28) |
| 150 | /* Enable cache. */ |
| 151 | movl %cr0, %eax |
| 152 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 153 | movl %eax, %cr0 |
| 154 | |
| 155 | /* Setup the stack. */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 156 | mov $_ecar_stack, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 157 | |
| 158 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 159 | the pushes below. */ |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 160 | andl $0xfffffff0, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 161 | subl $4, %esp |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 162 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 163 | /* push TSC and BIST to stack */ |
| 164 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 165 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 166 | movd %mm2, %eax |
| 167 | pushl %eax /* tsc[63:32] */ |
| 168 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 169 | pushl %eax /* tsc[31:0] */ |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 170 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 171 | before_c_entry: |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 172 | post_code(0x29) |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 173 | call bootblock_c_entry_bist |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 174 | |
| 175 | /* Should never see this postcode */ |
| 176 | post_code(POST_DEAD_CODE) |
| 177 | |
| 178 | .Lhlt: |
| 179 | hlt |
| 180 | jmp .Lhlt |
| 181 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 182 | fixed_mtrr_list: |
| 183 | .word MTRR_FIX_64K_00000 |
| 184 | .word MTRR_FIX_16K_80000 |
| 185 | .word MTRR_FIX_16K_A0000 |
| 186 | .word MTRR_FIX_4K_C0000 |
| 187 | .word MTRR_FIX_4K_C8000 |
| 188 | .word MTRR_FIX_4K_D0000 |
| 189 | .word MTRR_FIX_4K_D8000 |
| 190 | .word MTRR_FIX_4K_E0000 |
| 191 | .word MTRR_FIX_4K_E8000 |
| 192 | .word MTRR_FIX_4K_F0000 |
| 193 | .word MTRR_FIX_4K_F8000 |
| 194 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 195 | |
| 196 | _cache_as_ram_setup_end: |