Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 3 | |
| 4 | #include <cpu/x86/mtrr.h> |
| 5 | #include <cpu/x86/cache.h> |
| 6 | #include <cpu/x86/post_code.h> |
| 7 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 8 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 9 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 10 | |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 11 | #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) |
| 12 | #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" |
| 13 | #endif |
| 14 | #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 15 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 16 | .global bootblock_pre_c_entry |
| 17 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 18 | .code32 |
| 19 | _cache_as_ram_setup: |
| 20 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 21 | bootblock_pre_c_entry: |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 22 | |
| 23 | cache_as_ram: |
| 24 | post_code(0x20) |
| 25 | |
| 26 | /* Send INIT IPI to all excluding ourself. */ |
| 27 | movl $0x000C4500, %eax |
| 28 | movl $0xFEE00300, %esi |
| 29 | movl %eax, (%esi) |
| 30 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 31 | /* All CPUs need to be in Wait for SIPI state */ |
| 32 | wait_for_sipi: |
| 33 | movl (%esi), %eax |
| 34 | bt $12, %eax |
| 35 | jc wait_for_sipi |
| 36 | |
| 37 | post_code(0x22) |
| 38 | |
| 39 | /* Clear/disable fixed MTRRs */ |
| 40 | mov $fixed_mtrr_list_size, %ebx |
| 41 | xor %eax, %eax |
| 42 | xor %edx, %edx |
| 43 | |
| 44 | clear_fixed_mtrr: |
| 45 | add $-2, %ebx |
| 46 | movzwl fixed_mtrr_list(%ebx), %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 47 | wrmsr |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 48 | jnz clear_fixed_mtrr |
| 49 | |
Elyes HAOUAS | 02820ca | 2018-09-30 07:44:39 +0200 | [diff] [blame] | 50 | /* Figure out how many MTRRs we have, and clear them out */ |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 51 | mov $MTRR_CAP_MSR, %ecx |
| 52 | rdmsr |
| 53 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 54 | mov $MTRR_PHYS_BASE(0), %ecx |
| 55 | xor %eax, %eax |
| 56 | xor %edx, %edx |
| 57 | |
| 58 | clear_var_mtrr: |
| 59 | wrmsr |
| 60 | inc %ecx |
| 61 | wrmsr |
| 62 | inc %ecx |
| 63 | dec %ebx |
| 64 | jnz clear_var_mtrr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 65 | |
| 66 | post_code(0x22) |
| 67 | /* Configure the default memory type to uncacheable. */ |
| 68 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 69 | rdmsr |
| 70 | andl $(~0x00000cff), %eax |
| 71 | wrmsr |
| 72 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 73 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
| 74 | movl $0x80000008, %eax |
| 75 | cpuid |
| 76 | movb %al, %cl |
| 77 | sub $32, %cl |
| 78 | movl $1, %edx |
| 79 | shl %cl, %edx |
| 80 | subl $1, %edx |
| 81 | |
| 82 | /* Preload high word of address mask (in %edx) for Variable |
| 83 | MTRRs 0 and 1. */ |
| 84 | addrsize_set_high: |
| 85 | xorl %eax, %eax |
| 86 | movl $MTRR_PHYS_MASK(0), %ecx |
| 87 | wrmsr |
| 88 | movl $MTRR_PHYS_MASK(1), %ecx |
| 89 | wrmsr |
| 90 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 91 | post_code(0x23) |
| 92 | /* Set Cache-as-RAM base address. */ |
| 93 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 94 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 95 | xorl %edx, %edx |
| 96 | wrmsr |
| 97 | |
| 98 | post_code(0x24) |
| 99 | /* Set Cache-as-RAM mask. */ |
| 100 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 101 | rdmsr |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 102 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 103 | wrmsr |
| 104 | |
| 105 | post_code(0x25) |
| 106 | |
| 107 | /* Enable MTRR. */ |
| 108 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 109 | rdmsr |
| 110 | orl $MTRR_DEF_TYPE_EN, %eax |
| 111 | wrmsr |
| 112 | |
| 113 | /* Enable L2 cache. */ |
| 114 | movl $0x11e, %ecx |
| 115 | rdmsr |
| 116 | orl $(1 << 8), %eax |
| 117 | wrmsr |
| 118 | |
| 119 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 120 | movl %cr0, %eax |
| 121 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 122 | invd |
| 123 | movl %eax, %cr0 |
| 124 | |
| 125 | /* Clear the cache memory region. This will also fill up the cache. */ |
| 126 | movl $CACHE_AS_RAM_BASE, %esi |
| 127 | movl %esi, %edi |
| 128 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 129 | xorl %eax, %eax |
| 130 | rep stosl |
| 131 | |
| 132 | post_code(0x26) |
| 133 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 134 | movl %cr0, %eax |
| 135 | orl $CR0_CacheDisable, %eax |
| 136 | movl %eax, %cr0 |
| 137 | |
| 138 | /* Enable cache for our code in Flash because we do XIP here */ |
| 139 | movl $MTRR_PHYS_BASE(1), %ecx |
| 140 | xorl %edx, %edx |
| 141 | /* |
| 142 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
Stefan Tauner | de02878 | 2018-08-19 20:02:05 +0200 | [diff] [blame] | 143 | * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 144 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 145 | movl $_program, %eax |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 146 | andl $(~(XIP_ROM_SIZE - 1)), %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 147 | orl $MTRR_TYPE_WRPROT, %eax |
| 148 | wrmsr |
| 149 | |
| 150 | movl $MTRR_PHYS_MASK(1), %ecx |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 151 | rdmsr |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 152 | movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 153 | wrmsr |
| 154 | |
| 155 | post_code(0x28) |
| 156 | /* Enable cache. */ |
| 157 | movl %cr0, %eax |
| 158 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 159 | movl %eax, %cr0 |
| 160 | |
| 161 | /* Setup the stack. */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 162 | mov $_ecar_stack, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 163 | |
| 164 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 165 | the pushes below. */ |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 166 | andl $0xfffffff0, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 167 | subl $4, %esp |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 168 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 169 | /* push TSC and BIST to stack */ |
| 170 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 171 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 172 | movd %mm2, %eax |
| 173 | pushl %eax /* tsc[63:32] */ |
| 174 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 175 | pushl %eax /* tsc[31:0] */ |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 176 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 177 | before_c_entry: |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 178 | post_code(0x29) |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 179 | call bootblock_c_entry_bist |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 180 | |
| 181 | /* Should never see this postcode */ |
| 182 | post_code(POST_DEAD_CODE) |
| 183 | |
| 184 | .Lhlt: |
| 185 | hlt |
| 186 | jmp .Lhlt |
| 187 | |
Arthur Heymans | 3aa9adb | 2018-06-03 11:02:54 +0200 | [diff] [blame] | 188 | fixed_mtrr_list: |
| 189 | .word MTRR_FIX_64K_00000 |
| 190 | .word MTRR_FIX_16K_80000 |
| 191 | .word MTRR_FIX_16K_A0000 |
| 192 | .word MTRR_FIX_4K_C0000 |
| 193 | .word MTRR_FIX_4K_C8000 |
| 194 | .word MTRR_FIX_4K_D0000 |
| 195 | .word MTRR_FIX_4K_D8000 |
| 196 | .word MTRR_FIX_4K_E0000 |
| 197 | .word MTRR_FIX_4K_E8000 |
| 198 | .word MTRR_FIX_4K_F0000 |
| 199 | .word MTRR_FIX_4K_F8000 |
| 200 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 201 | |
| 202 | _cache_as_ram_setup_end: |