Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 16 | #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 17 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 18 | /* Device ID for SandyBridge and IvyBridge */ |
| 19 | #define BASE_REV_SNB 0x00 |
| 20 | #define BASE_REV_IVB 0x50 |
| 21 | #define BASE_REV_MASK 0x50 |
| 22 | |
| 23 | /* SandyBridge CPU stepping */ |
| 24 | #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ |
| 25 | #define SNB_STEP_D1 (BASE_REV_SNB + 6) |
| 26 | #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ |
| 27 | |
| 28 | /* IvyBridge CPU stepping */ |
| 29 | #define IVB_STEP_A0 (BASE_REV_IVB + 0) |
| 30 | #define IVB_STEP_B0 (BASE_REV_IVB + 2) |
| 31 | #define IVB_STEP_C0 (BASE_REV_IVB + 4) |
| 32 | #define IVB_STEP_K0 (BASE_REV_IVB + 5) |
| 33 | #define IVB_STEP_D0 (BASE_REV_IVB + 6) |
| 34 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 35 | /* Northbridge BARs */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 36 | #ifndef __ACPI__ |
| 37 | #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ |
| 38 | #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ |
| 39 | #else |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 40 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 41 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 42 | #endif |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 43 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 44 | #define DEFAULT_RCBABASE ((u8 *)0xfed1c000) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 46 | #define IOMMU_BASE1 0xfed90000ULL |
| 47 | #define IOMMU_BASE2 0xfed91000ULL |
| 48 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 49 | /* Everything below this line is ignored in the DSDT */ |
| 50 | #ifndef __ACPI__ |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 51 | #include <cpu/intel/model_206ax/model_206ax.h> |
| 52 | |
| 53 | /* Chipset types */ |
| 54 | enum platform_type { |
| 55 | PLATFORM_MOBILE = 0, |
| 56 | PLATFORM_DESKTOP_SERVER, |
| 57 | }; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 58 | |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 59 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 60 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 61 | |
| 62 | #define EPBAR 0x40 |
| 63 | #define MCHBAR 0x48 |
| 64 | #define PCIEXBAR 0x60 |
| 65 | #define DMIBAR 0x68 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 66 | |
| 67 | #define GGC 0x50 /* GMCH Graphics Control */ |
| 68 | |
| 69 | #define DEVEN 0x54 /* Device Enable */ |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 70 | #define DEVEN_D7EN (1 << 14) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 71 | #define DEVEN_PEG60 (1 << 13) |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 72 | #define DEVEN_D4EN (1 << 7) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 73 | #define DEVEN_IGD (1 << 4) |
| 74 | #define DEVEN_PEG10 (1 << 3) |
| 75 | #define DEVEN_PEG11 (1 << 2) |
| 76 | #define DEVEN_PEG12 (1 << 1) |
| 77 | #define DEVEN_HOST (1 << 0) |
| 78 | |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 79 | #define PAVPC 0x58 /* Protected Audio Video Path Control */ |
| 80 | #define DPR 0x5c /* DMA Protected Range */ |
| 81 | |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 82 | #define MESEG_BASE 0x70 |
| 83 | #define MESEG_MASK 0x78 |
Felix Held | f54ae38 | 2019-12-30 18:18:02 +0100 | [diff] [blame] | 84 | #define MELCK (1 << 10) /* ME Range Lock */ |
| 85 | #define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ |
Felix Held | bc3668a | 2019-12-28 18:44:06 +0100 | [diff] [blame] | 86 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 87 | #define PAM0 0x80 |
| 88 | #define PAM1 0x81 |
| 89 | #define PAM2 0x82 |
| 90 | #define PAM3 0x83 |
| 91 | #define PAM4 0x84 |
| 92 | #define PAM5 0x85 |
| 93 | #define PAM6 0x86 |
| 94 | |
| 95 | #define LAC 0x87 /* Legacy Access Control */ |
| 96 | #define SMRAM 0x88 /* System Management RAM Control */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 97 | |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 98 | #define REMAPBASE 0x90 |
| 99 | #define REMAPLIMIT 0x98 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 100 | #define TOM 0xa0 |
| 101 | #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 102 | #define BDSM 0xb0 /* Base Data of Stolen Memory */ |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 103 | #define BGSM 0xb4 /* Base GTT Stolen Memory */ |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 104 | #define TSEGMB 0xb8 /* TSEG Memory Base */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 105 | #define TOLUD 0xbc /* Top of Low Used Memory */ |
| 106 | |
Patrick Rudolph | 9f3f915 | 2016-01-26 20:02:14 +0100 | [diff] [blame] | 107 | #define CAPID0_A 0xe4 /* Capabilities Register A */ |
| 108 | #define CAPID0_B 0xe8 /* Capabilities Register B */ |
| 109 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 110 | #define SKPAD 0xdc /* Scratchpad Data */ |
| 111 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 112 | |
| 113 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 114 | |
| 115 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 116 | |
| 117 | /* |
| 118 | * MCHBAR |
| 119 | */ |
| 120 | |
Felix Held | b9267f0 | 2018-07-28 14:49:31 +0200 | [diff] [blame] | 121 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 122 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 123 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) |
Felix Held | fe68a77 | 2018-07-29 21:30:54 +0200 | [diff] [blame] | 124 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) |
| 125 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) |
Angel Pons | 26be0bd | 2019-12-31 14:29:48 +0100 | [diff] [blame] | 126 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 127 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 128 | /* Indexed register helper macros */ |
Felix Held | 9903565 | 2020-01-26 01:02:00 +0100 | [diff] [blame] | 129 | #define Gz(r, z) ((r) + ((z) << 8)) |
| 130 | #define Ly(r, y) ((r) + ((y) << 2)) |
| 131 | #define Cx(r, x) ((r) + ((x) << 10)) |
| 132 | #define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) |
| 133 | #define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 134 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 135 | /* byte lane training register base addresses */ |
| 136 | #define LANEBASE_B0 0x0000 |
| 137 | #define LANEBASE_B1 0x0200 |
| 138 | #define LANEBASE_B2 0x0400 |
| 139 | #define LANEBASE_B3 0x0600 |
Felix Held | aa30d62 | 2020-01-15 14:40:14 +0100 | [diff] [blame] | 140 | #define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 141 | #define LANEBASE_B4 0x1000 |
| 142 | #define LANEBASE_B5 0x1200 |
| 143 | #define LANEBASE_B6 0x1400 |
| 144 | #define LANEBASE_B7 0x1600 |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 145 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 146 | /* byte lane register offsets */ |
| 147 | #define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ |
| 148 | #define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ |
| 149 | #define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ |
| 150 | #define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ |
| 151 | #define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ |
| 152 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 153 | /* Register definitions */ |
| 154 | #define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ |
| 155 | #define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ |
| 156 | #define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch) /* PI coding for DDR CLK pins */ |
| 157 | #define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch) /* Logic delay of 1 QCLK in CLK slice */ |
| 158 | #define GDDLLFUSE_ch(ch) Gz(0x0c20, ch) /* Used for fuse download to the DLLs */ |
| 159 | #define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch) /* Debug MUX control */ |
| 160 | |
| 161 | #define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch) /* Debug MUX control */ |
| 162 | |
| 163 | #define CRCOMPOFST1_ch(ch) Gz(0x1810, ch) /* DQ, CTL and CLK Offset values */ |
| 164 | |
| 165 | #define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch) /* Data training mode control */ |
| 166 | #define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch) /* Training results according to PI */ |
| 167 | #define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch) |
| 168 | |
| 169 | #define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch) /* Indicates which rank is populated */ |
| 170 | #define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch) /* COMP values register */ |
| 171 | #define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch) /* COMP values register */ |
| 172 | #define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch) /* Command and control PI coding */ |
| 173 | |
| 174 | #define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ |
| 175 | #define GDCRDATACOMP 0x340c /* COMP values register */ |
| 176 | |
| 177 | #define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ |
| 178 | |
| 179 | /* MC per-channel registers */ |
| 180 | #define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ |
| 181 | #define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ |
| 182 | #define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ |
| 183 | #define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ |
| 184 | #define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ |
| 185 | #define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ |
| 186 | #define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ |
| 187 | #define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch) /* IO Latency Configuration */ |
| 188 | #define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch) /* Scrambling seed 1 */ |
| 189 | #define SCRAMBLING_SEED_2_LOW_ch(ch) Cx(0x4038, ch) /* Scrambling seed 2 low */ |
| 190 | #define SCRAMBLING_SEED_2_HIGH_ch(ch) Cx(0x403c, ch) /* Scrambling seed 2 high */ |
| 191 | |
| 192 | /* IOSAV Bytelane Bit-wise error */ |
| 193 | #define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y) |
| 194 | |
| 195 | /* IOSAV Bytelane Bit-wise compare mask */ |
| 196 | #define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y) |
| 197 | |
| 198 | /* |
| 199 | * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. |
| 200 | * Different counters for transactions that are issued on the ring agents (core or GT) and |
| 201 | * transactions issued in the SA. |
| 202 | */ |
| 203 | #define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch) |
| 204 | #define SC_PCIT_ch(ch) Cx(0x40ac, ch) /* Page-close idle timer setup - 8 bits */ |
| 205 | #define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch) /* Power-down (CKE-off) operation config */ |
| 206 | #define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch) /* ECC error injection count */ |
| 207 | #define ECC_DFT_ch(ch) Cx(0x40b8, ch) /* ECC DFT features (ECC4ANA, error inject) */ |
| 208 | #define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch) /* Extra WR delay to overcome WR-flyby issue */ |
| 209 | |
| 210 | #define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ |
| 211 | |
| 212 | /* IOSAV sub-sequence control registers */ |
Felix Held | 331d71b | 2020-01-14 15:57:18 +0100 | [diff] [blame] | 213 | #define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ |
| 214 | #define IOSAV_n_ADDR_UPD_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ |
| 215 | #define IOSAV_n_SP_CMD_CTL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ |
| 216 | #define IOSAV_n_SUBSEQ_CTL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ |
| 217 | #define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 218 | |
| 219 | #define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ |
| 220 | #define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ |
| 221 | #define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch) /* Data control in IOSAV mode */ |
| 222 | #define IOSAV_STATUS_ch(ch) Cx(0x428c, ch) /* State of the IOSAV sequence machine */ |
| 223 | #define TC_ZQCAL_ch(ch) Cx(0x4290, ch) /* ZQCAL control register */ |
| 224 | #define TC_RFP_ch(ch) Cx(0x4294, ch) /* Refresh Parameters */ |
| 225 | #define TC_RFTP_ch(ch) Cx(0x4298, ch) /* Refresh Timing Parameters */ |
| 226 | #define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch) /* MR2 shadow - copy of DDR configuration */ |
| 227 | #define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch) /* IOSAV mode control */ |
| 228 | #define TC_SRFTP_ch(ch) Cx(0x42a4, ch) /* Self-refresh timing parameters */ |
| 229 | #define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch) /* Data vector count of the first error */ |
| 230 | #define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch) /* IOSAV data check masking */ |
| 231 | |
| 232 | #define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y) /* Per-byte 16-bit error count */ |
| 233 | #define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch) /* Global 16-bit error count */ |
| 234 | |
| 235 | #define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch) /* Thermal mode configuration */ |
| 236 | #define PM_CMD_PWR_ch(ch) Cx(0x4384, ch) /* Power contribution of commands */ |
| 237 | #define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch) /* Bandwidth throttling on overtemp */ |
| 238 | #define SC_WDBWM_ch(ch) Cx(0x438c, ch) /* Watermarks and starvation counter */ |
| 239 | |
| 240 | /* MC Channel Broadcast registers */ |
| 241 | #define TC_DBP 0x4c00 /* Timings: BIN */ |
| 242 | #define TC_RAP 0x4c04 /* Timings: Regular access */ |
| 243 | #define TC_RWP 0x4c08 /* Timings: Read / Write */ |
| 244 | #define TC_OTHP 0x4c0c /* Timings: Other parameters */ |
| 245 | #define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ |
| 246 | #define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ |
| 247 | #define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ |
| 248 | #define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ |
| 249 | #define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ |
| 250 | #define SCRAMBLING_SEED_2_LOW 0x4c38 /* Scrambling seed 2 low */ |
| 251 | #define SCRAMBLING_SEED_2_HIGH 0x4c3c /* Scrambling seed 2 high */ |
| 252 | |
| 253 | #define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ |
| 254 | #define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ |
| 255 | |
| 256 | /* |
| 257 | * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. |
| 258 | * Different counters for transactions that are issued on the ring agents (core or GT) and |
| 259 | * transactions issued in the SA. |
| 260 | */ |
| 261 | #define SC_PR_CNT_CONFIG 0x4ca8 |
| 262 | #define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ |
| 263 | #define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ |
| 264 | #define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ |
| 265 | #define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ |
| 266 | #define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ |
| 267 | |
| 268 | /* Opportunistic reads configuration during write-major-mode (WMM) */ |
| 269 | #define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ |
| 270 | |
| 271 | #define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ |
| 272 | |
| 273 | #define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */ |
| 274 | #define IOSAV_n_ADDR_UPD(n) Ly(0x4e10, n) /* Address update after command execution */ |
| 275 | #define IOSAV_n_SP_CMD_CTL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */ |
| 276 | #define IOSAV_n_SUBSEQ_CTL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */ |
| 277 | #define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */ |
| 278 | |
| 279 | #define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ |
| 280 | #define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ |
| 281 | #define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ |
| 282 | #define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ |
| 283 | #define TC_ZQCAL 0x4e90 /* ZQCAL control register */ |
| 284 | #define TC_RFP 0x4e94 /* Refresh Parameters */ |
| 285 | #define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ |
| 286 | #define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ |
| 287 | #define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ |
| 288 | #define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ |
| 289 | |
| 290 | /* |
| 291 | * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this |
| 292 | * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. |
| 293 | */ |
| 294 | #define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ |
| 295 | |
| 296 | #define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ |
| 297 | #define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ |
| 298 | |
| 299 | #define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ |
| 300 | #define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ |
| 301 | |
| 302 | #define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ |
| 303 | #define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ |
| 304 | #define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ |
| 305 | #define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ |
| 306 | |
| 307 | #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ |
| 308 | #define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ |
| 309 | #define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ |
| 310 | #define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on SNB) */ |
| 311 | #define MAD_ZR 0x5014 /* Address Decode Zones */ |
| 312 | #define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ |
| 313 | #define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ |
| 314 | |
| 315 | #define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ |
| 316 | |
| 317 | #define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ |
| 318 | #define MRC_REVISION 0x5034 /* MRC Revision */ |
| 319 | #define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ |
| 320 | #define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ |
| 321 | |
| 322 | #define MC_LOCK 0x50fc /* Memory Controlller Lock register */ |
| 323 | |
| 324 | #define VTD1_BASE 0x5400 /* Base address for IGD */ |
| 325 | #define VTD2_BASE 0x5410 /* Base address for PEG, USB, SATA, etc. */ |
| 326 | #define PAIR_CTL 0x5418 /* Power Aware Interrupt Routing Control */ |
| 327 | |
| 328 | /* PAVP control register, undocumented. Different from PAVPC on PCI config space. */ |
| 329 | #define MMIO_PAVP_CTL 0x5500 /* Bit 0 locks PAVP settings */ |
| 330 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 331 | #define MEM_TRML_ESTIMATION_CONFIG 0x5880 |
| 332 | #define MEM_TRML_THRESHOLDS_CONFIG 0x5888 |
Angel Pons | 26be0bd | 2019-12-31 14:29:48 +0100 | [diff] [blame] | 333 | #define MEM_TRML_INTERRUPT 0x58a8 |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 334 | |
| 335 | #define MC_TURBO_PL1 0x59a0 /* Turbo Power Limit 1 parameters */ |
| 336 | #define MC_TURBO_PL2 0x59a4 /* Turbo Power Limit 2 parameters */ |
| 337 | |
| 338 | #define SSKPD_OK 0x5d10 /* 64-bit scratchpad register */ |
| 339 | #define SSKPD 0x5d14 /* 16bit (scratchpad) */ |
| 340 | #define BIOS_RESET_CPL 0x5da8 /* 8bit */ |
| 341 | |
| 342 | /* PCODE will sample SAPM-related registers at the end of Phase 4. */ |
| 343 | #define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ |
| 344 | #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ |
| 345 | #define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ |
| 346 | #define M_COMP 0x5f08 /* Memory COMP control */ |
| 347 | #define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ |
| 348 | |
| 349 | /* WARNING: Only applies to Sandy Bridge! */ |
| 350 | #define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ |
| 351 | |
| 352 | /** WARNING: Only applies to Ivy Bridge! */ |
| 353 | #define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ |
| 354 | #define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 355 | |
| 356 | /* |
| 357 | * EPBAR - Egress Port Root Complex Register Block |
| 358 | */ |
| 359 | |
Felix Held | b9267f0 | 2018-07-28 14:49:31 +0200 | [diff] [blame] | 360 | #define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) |
| 361 | #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) |
| 362 | #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 363 | |
| 364 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 365 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 366 | |
| 367 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 368 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 369 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 370 | |
| 371 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 372 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 373 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 374 | |
| 375 | #define EPVC1MTS 0x028 /* 32bit */ |
| 376 | #define EPVC1IST 0x038 /* 64bit */ |
| 377 | |
| 378 | #define EPESD 0x044 /* 32bit */ |
| 379 | |
| 380 | #define EPLE1D 0x050 /* 32bit */ |
| 381 | #define EPLE1A 0x058 /* 64bit */ |
| 382 | #define EPLE2D 0x060 /* 32bit */ |
| 383 | #define EPLE2A 0x068 /* 64bit */ |
| 384 | |
| 385 | #define PORTARB 0x100 /* 256bit */ |
| 386 | |
| 387 | /* |
| 388 | * DMIBAR |
| 389 | */ |
| 390 | |
Felix Held | b9267f0 | 2018-07-28 14:49:31 +0200 | [diff] [blame] | 391 | #define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) |
| 392 | #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) |
| 393 | #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 394 | |
| 395 | #define DMIVCECH 0x000 /* 32bit */ |
| 396 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 397 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 398 | |
| 399 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 400 | |
| 401 | #define DMIVC0RCAP 0x010 /* 32bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 402 | #define DMIVC0RCTL 0x014 /* 32bit */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 403 | #define DMIVC0RSTS 0x01a /* 16bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 404 | #define VC0NP 0x2 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 405 | |
| 406 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 407 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 408 | #define DMIVC1RSTS 0x026 /* 16bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 409 | #define VC1NP 0x2 |
| 410 | |
| 411 | #define DMIVCPRCTL 0x02c /* 32bit */ |
| 412 | |
| 413 | #define DMIVCPRSTS 0x032 /* 16bit */ |
| 414 | #define VCPNP 0x2 |
| 415 | |
| 416 | #define DMIVCMRCTL 0x0038 /* 32 bit */ |
| 417 | #define DMIVCMRSTS 0x003e /* 16 bit */ |
| 418 | #define VCMNP 0x2 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 419 | |
| 420 | #define DMILE1D 0x050 /* 32bit */ |
| 421 | #define DMILE1A 0x058 /* 64bit */ |
| 422 | #define DMILE2D 0x060 /* 32bit */ |
| 423 | #define DMILE2A 0x068 /* 64bit */ |
| 424 | |
| 425 | #define DMILCAP 0x084 /* 32bit */ |
| 426 | #define DMILCTL 0x088 /* 16bit */ |
| 427 | #define DMILSTS 0x08a /* 16bit */ |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 428 | #define TXTRN (1 << 11) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 429 | #define DMICTL1 0x0f0 /* 32bit */ |
| 430 | #define DMICTL2 0x0fc /* 32bit */ |
| 431 | |
| 432 | #define DMICC 0x208 /* 32bit */ |
| 433 | |
| 434 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 435 | |
| 436 | #ifndef __ASSEMBLER__ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 437 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 438 | void intel_sandybridge_finalize_smm(void); |
Kyösti Mälkki | 82c0e7e | 2019-11-05 19:06:56 +0200 | [diff] [blame] | 439 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 440 | int bridge_silicon_revision(void); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 441 | void systemagent_early_init(void); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 442 | void sandybridge_init_iommu(void); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 443 | void sandybridge_late_initialization(void); |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 444 | void northbridge_romstage_finalize(int s3resume); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 445 | void early_init_dmi(void); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 446 | |
Arthur Heymans | dc2e7c6 | 2019-11-12 16:17:26 +0100 | [diff] [blame] | 447 | /* mainboard_early_init: Optional mainboard callback run after console init |
| 448 | but before raminit. */ |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 449 | void mainboard_early_init(int s3resume); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 450 | int mainboard_should_reset_usb(int s3resume); |
| 451 | void perform_raminit(int s3resume); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 452 | enum platform_type get_platform_type(void); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 453 | |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 454 | #include <device/device.h> |
| 455 | |
| 456 | struct acpi_rsdp; |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 457 | unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 458 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 459 | #endif |
| 460 | #endif |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 461 | #endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ |